Conferences related to MIM capacitors

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2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2020 IEEE International Magnetic Conference (INTERMAG)

INTERMAG is the premier conference on all aspects of applied magnetism and provides a range of oral and poster presentations, invited talks and symposia, a tutorial session, and exhibits reviewing the latest developments in magnetism.


2020 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges


2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


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Periodicals related to MIM capacitors

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Antennas and Propagation, IEEE Transactions on

Experimental and theoretical advances in antennas including design and development, and in the propagation of electromagnetic waves including scattering, diffraction and interaction with continuous media; and applications pertinent to antennas and propagation, such as remote sensing, applied optics, and millimeter and submillimeter wave techniques.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Components and Packaging Technologies, IEEE Transactions on

Component parts, hybrid microelectronics, materials, packaging techniques, and manufacturing technology.


Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Dielectrics and Electrical Insulation, IEEE Transactions on

Electrical insulation common to the design and construction of components and equipment for use in electric and electronic circuits and distribution systems at all frequencies.


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Most published Xplore authors for MIM capacitors

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Xplore Articles related to MIM capacitors

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Effect of Nitrogen Passivation on the Performance of MIM Capacitors With a Crystalline-<formula formulatype="inline"><tex Notation="TeX">$\hbox{TiO}_{2}/\hbox{SiO}_{2}$</tex></formula>Stacked Insulator

IEEE Electron Device Letters, 2012

TiO2/SiO2stacked dielectric-based metal-insulator-metal capacitors with different thermal and nitrogen plasma treatments (NPTs) were explored in this letter. As the TiO2dielectric crystallizes from amorphous phase after a thermal treatment, capacitance density increasing from 7.7 to 11.9 fF/m2was obtained at the price of aggravating leakage current and wider distribution in device characteristics. With NPT to well passivate grain-boundary-related defects in the crystalline ...


A DRAM technology using MIM BST capacitor for 0.15 /spl mu/m DRAM generation and beyond

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325), 1999

Recently, 1 Gb DRAM based on the 0.18 /spl mu/m technology node (generation) and 0.15 /spl mu/m technology node for 4 Gb DRAM have been successfully demonstrated. These two technology generations are based on MIS capacitors using Ta/sub 2/O/sub 5/ dielectric. The extension of Ta/sub 2/O/sub 5/ MIS capacitors below 0.15 /spl mu/m technology is considered to be difficult due ...


A model for discretization error in electromagnetic analysis of capacitors

IEEE Transactions on Microwave Theory and Techniques, 1998

The error due to discretization in a method-of-moments analysis of a parallel plate or metal-insulator-metal (MIM) capacitor is discussed. A technique related to Richardson extrapolation is used to develop a model for the error due to subsectional discretization. The results are for Galerkin's method using rooftop basis functions; however, the technique can be applied to any variational moment-method calculation. An ...


Three-dimensional 35 nF/mm/sup 2/ MIM capacitors integrated in BiCMOS technology

Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005., 2005

Decoupling applications require high capacitance values. To optimize the chip performances, it appears particularly interesting to integrate them directly in interconnect levels, especially in BiCMOS technology. In order to reach this goal and minimize the area occupied by such devices, three-dimensional MiM capacitors have been introduced with different dielectrics: Ta/sub 2/O/sub 5/ deposited by MOCVD and A1/sub 2/O/sub 3/ by ...


Complex Permittivity Determination of Thin-Films Through RF-Measurements of a MIM Capacitor

IEEE Microwave and Wireless Components Letters, 2014

A method for determining the permittivity and loss tangent of thin-film layers is presented. The method relies on the measurement of the reflection coefficient to a single metal-insulator-metal (MIM) structure without requiring additional de-embedding dummy structures to account for the test- fixture parasitics. Results allow to obtain the frequency-dependent dielectric parameters, whereas the impact of the test-fixture parasitics is quantified ...


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Educational Resources on MIM capacitors

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IEEE-USA E-Books

  • Effect of Nitrogen Passivation on the Performance of MIM Capacitors With a Crystalline-<formula formulatype="inline"><tex Notation="TeX">$\hbox{TiO}_{2}/\hbox{SiO}_{2}$</tex></formula>Stacked Insulator

    TiO2/SiO2stacked dielectric-based metal-insulator-metal capacitors with different thermal and nitrogen plasma treatments (NPTs) were explored in this letter. As the TiO2dielectric crystallizes from amorphous phase after a thermal treatment, capacitance density increasing from 7.7 to 11.9 fF/m2was obtained at the price of aggravating leakage current and wider distribution in device characteristics. With NPT to well passivate grain-boundary-related defects in the crystalline TiO2film, devices still keep a satisfactory capacitance level of 11.2 fF/μm2while exhibiting suppressed leakage current by a factor of 53, a lower quadratic voltage coefficient of capacitance (VCC-α) of 30 ppm/V2, near frequency dispersion-free capacitance, a better temperature coefficient of capacitance of 82 ppm/°C, and more controllable device uniformity. The mechanism for the improved electrical characteristics was further confirmed by atomic force microscope. These results suggest that NPT paves a new avenue to further advance the performance of crystalline dielectric-based devices.

  • A DRAM technology using MIM BST capacitor for 0.15 /spl mu/m DRAM generation and beyond

    Recently, 1 Gb DRAM based on the 0.18 /spl mu/m technology node (generation) and 0.15 /spl mu/m technology node for 4 Gb DRAM have been successfully demonstrated. These two technology generations are based on MIS capacitors using Ta/sub 2/O/sub 5/ dielectric. The extension of Ta/sub 2/O/sub 5/ MIS capacitors below 0.15 /spl mu/m technology is considered to be difficult due to insufficient cell capacitance. It is widely accepted that the MIM capacitor using high dielectric constant material is inevitable for 0.15 /spl mu/m technology and beyond. Although many studies to use high dielectric material have been reported, those studies are not adequate for 0.15 /spl mu/m technology and beyond because most of the studies are either based on a simple capacitor module process or based on large feature size design rules. In this paper, for the first time, a DRAM technology using BaSrTiO/sub 3/ (BST) MIM capacitors is developed with 0.15 /spl mu/m technology.

  • A model for discretization error in electromagnetic analysis of capacitors

    The error due to discretization in a method-of-moments analysis of a parallel plate or metal-insulator-metal (MIM) capacitor is discussed. A technique related to Richardson extrapolation is used to develop a model for the error due to subsectional discretization. The results are for Galerkin's method using rooftop basis functions; however, the technique can be applied to any variational moment-method calculation. An expression is presented for the error in capacitance calculations, which is shown to hold for changes in geometry and dielectric constant. In addition, the expression for error is shown to be accurate for a wide range of meshing geometries. Surprisingly, the error model is not an upper bound, but rather is met nearly in equality for all geometries considered. Thus, the error may be simply subtracted from the calculated value for a more accurate result.

  • Three-dimensional 35 nF/mm/sup 2/ MIM capacitors integrated in BiCMOS technology

    Decoupling applications require high capacitance values. To optimize the chip performances, it appears particularly interesting to integrate them directly in interconnect levels, especially in BiCMOS technology. In order to reach this goal and minimize the area occupied by such devices, three-dimensional MiM capacitors have been introduced with different dielectrics: Ta/sub 2/O/sub 5/ deposited by MOCVD and A1/sub 2/O/sub 3/ by ALD. Thus, high capacitance density of 35nF/mm/sup 2/ has been reached. Through comparison between planar and three dimensional (3D) MIM capacitor characterization, it has been demonstrated that 3D MIM capacitor, named high density trench capacitor (HiDTC), architecture is a very promising candidate to integrate such high capacitance values.

  • Complex Permittivity Determination of Thin-Films Through RF-Measurements of a MIM Capacitor

    A method for determining the permittivity and loss tangent of thin-film layers is presented. The method relies on the measurement of the reflection coefficient to a single metal-insulator-metal (MIM) structure without requiring additional de-embedding dummy structures to account for the test- fixture parasitics. Results allow to obtain the frequency-dependent dielectric parameters, whereas the impact of the test-fixture parasitics is quantified by developing the corresponding equivalent circuit model. The accuracy of this model is verified by obtaining excellent simulation-experiment correlation of the MIM admittance at microwave frequencies.

  • Single poly EEPROM with N-well and stacked MIM capacitor for control gate

    The new structure of EEPROM is proposed for an excellent programming characteristic with a small cell-size. The capacitor of EEPROM is composed of a stacked MIM (Metal-Insulator-Metal) and n-well. A split-type floating gate is connected to these two capacitors in a single poly EEPROM. The TCAD simulation shows that the programming speed is controlled within 10<sup>-4</sup> sec. at coupling ratio of 0.75 and control gate voltage of 4 V. We obtain the threshold voltage shifts of 3.2 V between program and erase states.

  • A 5GHz resistive-feedback CMOS LNA for low-cost multi-standard applications

    A 5GHz broadband LNA achieves 25dB gain, 2dB NF, -14dBm IIP3 and -13dB S11 while drawing 15.5mA from a 2.7V supply. The circuit is fabricated in an RF- enhanced 90nm CMOS technology. The active die area is 0.025mm<sup>2</sup>

  • High-performance single polysilicon EEPROM with stacked MIM capacitor

    High-performance single polysilicon electrically erasable programmable read- only memories (EEPROMs) with stacked metal-insulator-metal capacitor as a control gate are investigated. The thickness of the tunnel oxide and the length of the floating gate channel of the fabricated devices were 52 /spl Aring/ and 0.24 μm, respectively. The effective control gate coupling ratio of the proposed EEPROM cell was higher than that of cells with n-well control gate because of the absence of depletion capacitance in the n-well silicon region. The experimental results showed that the program speed of the proposed cells were faster than those of the conventional n-well control gate cells. In addition, the proposed cells had threshold voltage shifts of 3.5 V between program and erase states. Furthermore, there were threshold voltage shifts of 3.0 V without degradation of the read currents after 1000 program/erase cycles.

  • High capacitance density (&gt; 17 fF//spl mu/m/sup 2/) Nb/sub 2/O/sub 5/-based MIM capacitors for future RF IC applications

    MIM capacitor with niobium pentoxide (Nb/sub 2/O/sub 5/) dielectric whose K value is higher than 40, is successfully demonstrated for RF bypass capacitor application. Nb/sub 2/O/sub 5/ MIM with HfO/sub 2//Al/sub 2/O/sub 3/ barriers delivers a record high capacitance density >17 fF//spl mu/m/sup 2/ with excellent reliability and RF properties, while maintaining comparable leakage current with other high-K dielectrics. It is demonstrated that the high capacitance values can be stable up to 20 GHz when it is integrated into Cu- BEOL process.

  • Cylindrical Ru-SrTiO/sub 3/-Ru capacitor technology for 0.11 /spl mu/m generation DRAMs

    We have developed a cylindrical Ru/ST/Ru capacitor for gigabit-scale DRAMs. Using cylindrical CVD-Ru as a storage node (SN), a new 2-step CVD-ST was employed to improve ST step coverage, surface morphology and to control composition at the Ru/ST interface. A SiO/sub 2/ equivalent thickness (t/sub eq/) of 0.6 nm and cell capacitance of 18 fF/cell with leakage current of 0.1 fA/cell at /spl plusmn/0.7 V applied voltage has been achieved on a 256K cylindrical Ru/ST/Ru capacitor array.



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