Conferences related to IEEE Computer Architecture Letters

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2020 IEEE International Symposium on Antennas and Propagation and North American Radio Science Meeting

The joint meeting is intended to provide an international forum for the exchange of information on state of the art research in the area of antennas and propagation, electromagnetic engineering and radio science


2019 IEEE 28th International Symposium on Industrial Electronics (ISIE)

The conference will provide a forum for discussions and presentations of advancements inknowledge, new methods and technologies relevant to industrial electronics, along with their applications and future developments.


2019 IEEE International Symposium on Medical Measurements and Applications (MeMeA)

The symposium deals with all the aspects of interactions among the worlds of the instrumentation and measurement, bio-engineering, material science, chemical and biological measurements, and the medical field. The symposium enables researchers, doctors and technicians to exchange ideas and information, make connections and collaborations and update innovation on health care systems and diagnostics in medicine.


2018 17th RoEduNet Conference: Networking in Education and Research (RoEduNet)

Nowadays, modern education and research activities are strongly dependent on a high-speed communication infrastructure and computer networks based on the newest technology. Design, implementation, management of such networks, together with development of new application fields are not possible without good knowledge of networking state-of-the-art.

  • 2017 16th RoEduNet Conference: Networking in Education and Research (RoEduNet)

    Nowadays, modern education and research activities are strongly dependent on a high-speed communication infrastructure and computer networks based on the newest technology. Design, implementation, management of such networks, together with development of new application fields are not possible without good knowledge of networking state-of-the-art.

  • 2016 15th RoEduNet Conference: Networking in Education and Research

    Nowadays, modern education and research activities are strongly dependent on a high-speed communication infrastructure and computer networks based on the newest technology. Design, implementation, management of such networks, together with development of new application fields are not possible without good knowledge of networking state-of-the-art.

  • 2015 14th RoEduNet International Conference - Networking in Education and Research (RoEduNet NER)

    Nowadays, modern education and research activities are strongly dependent on a high-speed communication infrastructure and computer networks based on the newest technology. Design, implementation, management of such networks, together with development of new applicationfields are not possible without good knowledge of networking state-of-the-art.

  • 2014 Joint Networking in Education and Research Conference (RoEduNet/RENAM)

    Nowadays, modern education and research activities are strongly dependent on a high-speed communication infrastructure and computer networks based on the newest technology. Design, implementation, management of such networks, together with development of new application fields are not possible without good knowledge of networking state-of-the-art.

  • 2013 RoEduNet International Conference 11th Edition: Networking in Education and Research

    The 11th edition of RoEduNet International Conference, organized in Sinaia by Agency ARNIEC/RoEduNet under the patronage of Ministry of Education, Research, Youth and Sports, offers special opportunities for information exchange in computer networking: technical and strategic aspects, communication issues, and of course their applications in education and research.

  • 2011 RoEduNet International Conference 10th Edition: Networking in Education and Research

    The 10th edition of RoEduNet International Conference, organized in Iasi by Agency ARNIEC Iasi under the patronage of Ministry of Education, Research, Youth and Sports, offers special opportunities for information exchange in computer networking: technical and strategic aspects, communication issues, and of course their applications in education and research.

  • 2010 9th Roedunet International Conference (RoEduNet)

    a major annual international conference organized with the objective of bringing together researchers, developers, and practitioners from academia and industry working in all areas of computer networking


2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)

Analog Circuits, Digital VLSI Circuits, Neural Networks, Non-Linear System, Computer Aided Design, Communication Systems, Digital Signal Processing, MEMS, Nano-electronics


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Periodicals related to IEEE Computer Architecture Letters

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Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Communications Letters, IEEE

Covers topics in the scope of IEEE Transactions on Communications but in the form of very brief publication (maximum of 6column lengths, including all diagrams and tables.)


Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


Computer Architecture Letters

Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing


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Most published Xplore authors for IEEE Computer Architecture Letters

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Xplore Articles related to IEEE Computer Architecture Letters

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Accelerator for Sparse Machine Learning

IEEE Computer Architecture Letters, 2018

Sparse matrix by vector multiplication (SpMV) plays a pivotal role in machine learning and data mining. We propose and investigate an SpMV accelerator, specifically designed to accelerate the sparse matrix by sparse vector multiplication (SpMSpV), and to be integrated in a CPU core. We show that our accelerator outperforms a similar solution by 70x while achieving 8x higher power efficiency, ...


Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors

IEEE Computer Architecture Letters, 2012

Traversing page table during virtual to physical address translation causes significant pipeline stalls when misses occur in the translation-lookaside buffer (TLB). To mitigate this penalty, we propose a fast, scalable, multi- level TLB organization that leverages page sharing behaviors and performs efficient TLB entry placement. Our proposed partial sharing TLB (PSTLB) reduces TLB misses by around 60%. PSTLB also improves ...


Weighted Random Routing on Torus Networks

IEEE Computer Architecture Letters, 2009

In this paper, we introduce a new closed-form oblivious routing algorithm called W2TURN that is worst-case throughput optimal for 2D-torus networks. W2TURN is based on a weighted random selection of paths that contain at most two turns. In terms of average hop count, W2TURN outperforms the best previously known closed-form worst-case throughput optimal routing algorithm called IVAL. In addition, we ...


Using Resampling Techniques to Compute Confidence Intervals for the Harmonic Mean of Rate-Based Performance Metrics

IEEE Computer Architecture Letters, 2010

Rate-based metrics such as floating point operations per second, instructions per cycle and so forth are commonly used to measure computer performance. In addition to the average or mean performance of the metric, indicating the precision of the mean using confidence intervals helps to make informed decisions and comparisons with the data. In this paper, we discuss the determination of ...


Demystifying multicore throughput metrics

IEEE Computer Architecture Letters, 2013

Several different metrics have been proposed for quantifying the throughput of multicore processors. There is no clear consensus about which metric should be used. Some studies even use several throughput metrics. We show that there exists a relation between single-thread average performance metrics and throughput metrics, and that throughput metrics inherit the meaning or lack of meaning of the corresponding ...


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Educational Resources on IEEE Computer Architecture Letters

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IEEE-USA E-Books

  • Accelerator for Sparse Machine Learning

    Sparse matrix by vector multiplication (SpMV) plays a pivotal role in machine learning and data mining. We propose and investigate an SpMV accelerator, specifically designed to accelerate the sparse matrix by sparse vector multiplication (SpMSpV), and to be integrated in a CPU core. We show that our accelerator outperforms a similar solution by 70x while achieving 8x higher power efficiency, which yields an estimated 29x energy reduction for SpMSpV based applications.

  • Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors

    Traversing page table during virtual to physical address translation causes significant pipeline stalls when misses occur in the translation-lookaside buffer (TLB). To mitigate this penalty, we propose a fast, scalable, multi- level TLB organization that leverages page sharing behaviors and performs efficient TLB entry placement. Our proposed partial sharing TLB (PSTLB) reduces TLB misses by around 60%. PSTLB also improves TLB performance by nearly 40% compared to traditional private TLBs and 17% over the state of the art scalable TLB proposal.

  • Weighted Random Routing on Torus Networks

    In this paper, we introduce a new closed-form oblivious routing algorithm called W2TURN that is worst-case throughput optimal for 2D-torus networks. W2TURN is based on a weighted random selection of paths that contain at most two turns. In terms of average hop count, W2TURN outperforms the best previously known closed-form worst-case throughput optimal routing algorithm called IVAL. In addition, we present a new optimal weighted random routing algorithm for rings called WRD.

  • Using Resampling Techniques to Compute Confidence Intervals for the Harmonic Mean of Rate-Based Performance Metrics

    Rate-based metrics such as floating point operations per second, instructions per cycle and so forth are commonly used to measure computer performance. In addition to the average or mean performance of the metric, indicating the precision of the mean using confidence intervals helps to make informed decisions and comparisons with the data. In this paper, we discuss the determination of confidence intervals for the harmonic mean of rate-based metrics using two statistical resampling techniques - Jackknife and Bootstrap. We show using Monte Carlo simulations that resampling indeed works as expected, and can be used for generating confidence intervals for harmonic mean.

  • Demystifying multicore throughput metrics

    Several different metrics have been proposed for quantifying the throughput of multicore processors. There is no clear consensus about which metric should be used. Some studies even use several throughput metrics. We show that there exists a relation between single-thread average performance metrics and throughput metrics, and that throughput metrics inherit the meaning or lack of meaning of the corresponding single-thread metric. We show that two popular throughput metrics, the weighted speedup and the harmonic mean of speedups, are inconsistent: they do not give equal importance to all benchmarks. Moreover we demonstrate that the weighted speedup favors unfairness. We show that the harmonic mean of IPCs, a seldom used throughput metric, is actually consistent and has a physical meaning. We explain under which conditions the arithmetic mean or the harmonic mean of IPCs can be used as a strong indicator of throughput increase.

  • Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction

    We compare techniques that dynamically scale the voltage of individual network links to reduce power consumption with an approach in which all links in the network are set to the same voltage and adaptive routing is used to distribute load across the network. Our results show that adaptive routing with static network link voltages outperforms dimension-order routing with dynamic link voltages in all cases, because the adaptive routing scheme can respond more quickly to changes in network demand. Adaptive routing with static link voltages also outperforms adaptive routing with dynamic link voltages in many cases, although dynamic link voltage scaling gives better behavior as the demand on the network grows.

  • Branch Misprediction Prediction: Complementary Branch Predictors

    In this paper, we propose a new class of branch predictors, complementary branch predictors, which can be easily added to any branch predictor to improve the overall prediction accuracy. This mechanism differs from conventional branch predictors in that it focuses only on mispredicted branches. As a result, this mechanism has the advantages of scalability and flexibility (can be implemented with any branch predictor), but is not on the critical path. More specifically, this mechanism improves the branch prediction accuracy by predicting which future branch will be mispredicted next and when that will occur, and then it changes the predicted direction at the predicted time. Our results show that a branch predictor with the branch misprediction predictor achieves the same prediction accuracy as a conventional branch predictor that is 4 to 16 times larger, but without significantly increasing the overall complexity or lengthening the critical path.

  • Resistive Associative Processor

    Associative Processor (AP) combines data storage and data processing, and functions simultaneously as a massively parallel array SIMD processor and memory. Traditionally, AP is based on CMOS technology, similar to other classes of massively parallel SIMD processors. The main component of AP is a Content Addressable Memory (CAM) array. As CMOS feature scaling slows down, CAM experiences scalability problems. In this work, we propose and investigate an AP based on resistive CAM-the Resistive AP (ReAP). We show that resistive memory technology potentially allows scaling the AP from a few millions to a few hundred millions of processing units on a single silicon die. We compare the performance and power consumption of a ReAP to a CMOS AP and a conventional SIMD accelerator (GPU) and show that ReAP, although exhibiting higher power density, allows better scalability and higher performance.

  • Diversity: A Design Goal for Heterogeneous Processors

    A growing number of processors have CPU cores that implement the same instruction set architecture (ISA) using different microarchitectures. The underlying motivation for single-ISA heterogeneity is that a diverse set of cores can enable runtime flexibility. Modern processors are subject to strict power budgets, and heterogeneity provides the runtime scheduler with more latitude to decide the level of performance a program should have based on the amount of power that can be spent. We argue that selecting a diverse set of heterogeneous cores to enable flexible operation at runtime is a non-trivial problem due to diversity in program behavior. We further show that common evaluation methods lead to false conclusions about diversity. Finally, we suggest the KS statistical test as an evaluation metric. The KS test is the first step toward a heterogeneous design methodology that optimizes for runtime flexibility.

  • Efficiently Evaluating Speedup Using Sampled Processor Simulation

    Cycle accurate simulation of processors is extremely time consuming. Sampling can greatly reduce simulation time while retaining good accuracy. Previous research on sampled simulation has been focusing on the accuracy of CPI. However, most simulations are used to evaluate the benefit of some microarchitectural enhancement, in which the speedup is a more important metric than CPI. We employ the ratio estimator from statistical sampling theory to design efficient sampling to measure speedup and to quantify its error. We show that to achieve a given relative error limit for speedup, it is not necessary to estimate CPI to the same accuracy. In our experiment, estimating speedup requires about 9X fewer instructions to be simulated in detail in comparison to estimating CPI for the same relative error limit. Therefore using the ratio estimator to evaluate speedup is much more cost- effective and offers great potential for reducing simulation time. We also discuss the reason for this interesting and important result.



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