Conferences related to Double-gate FETs

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2020 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC)

The conference program will consist of plenary lectures, symposia, workshops and invitedsessions of the latest significant findings and developments in all the major fields of biomedical engineering.Submitted papers will be peer reviewed. Accepted high quality papers will be presented in oral and postersessions, will appear in the Conference Proceedings and will be indexed in PubMed/MEDLINE


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2019 IEEE 9th International Nanoelectronics Conferences (INEC)

Topics of Interests (but not limited to)• Application of nanoelectronic• Low-dimensional materials• Microfluidics/Nanofluidics• Nanomagnetic materials• Carbon materials• Nanomaterials• Nanophotonics• MEMS/NEMS• Nanoelectronic• Nanomedicine• Nano Robotics• Spintronic devices• Sensor and actuators• Quality and Reliability of Nanotechnology


2019 IEEE International Conference on Electro Information Technology (EIT)

Robotics and MechatronicsGPU ComputingIntelligent Systems and Multi-agent SystemsControl Systems and System IdentificationReconfigurable and Embedded SystemsPower Systems and Power ElectronicsSolid State, Consumer and Automotive ElectronicsADAS-Advanced Driver Assist SystemsConnected Vehicle - V2V, V2I, V2XBiomedical Applications, TelemedicineBiometrics and BioinformaticsNanotech, Micro Electromechanical SystemsWireless communication, Sensor NetworksCyber SecurityComputer Vision, Signal/Image and ProcessingDistributed Data Fusion and Data MiningCloud, Mobile, and Distributed ComputingSoftware Engineering, Middleware ArchitectureEngineering Education


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Periodicals related to Double-gate FETs

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Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


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Most published Xplore authors for Double-gate FETs

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Xplore Articles related to Double-gate FETs

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Reliability of 4H-SiC DMOSFETs Evaluated by Bias Stressing

2007 65th Annual Device Research Conference, 2007

In this work, the threshold voltage (V<sub>TH</sub>) of n-channel 4H-SiC double-implanted metal-oxide- semiconductor field effect transistors (DMOSFETs) was measured after different gate-bias-stress durations to determine if the bias-stress induces a shift in the V<sub>TH</sub>.


Ballistic FET modeling using QDAME: quantum device analysis by modal evaluation

IEEE Transactions on Nanotechnology, 2002

We present an algorithm for self-consistent solution of the Poisson and Schrodinger equations in two spatial dimensions with open-boundary conditions to permit current flow. The algorithm works by discretely sampling a device's density of states using standing wave boundary conditions, decomposing the standing waves into traveling waves injected from the contacts to assign occupancies, and iterating the quantum charge with ...


Compound Semiconductor as CMOS Channel Material: Déjà vu or New Paradigm?

2008 Device Research Conference, 2008

We have examined the potential of double gate (DG) inter-band tunnel FETs (TFET) in 3 different material systems, Si, Ge and InAs, for logic circuit applications down to 0.25 V supply voltage (V<sub>CC</sub>). Based on the two- dimensional numerical drift-diffusion simulations, we conclude that 30 nm gate length InAs (indium arsenide) based TFETs can achieve I<sub>on</sub>/I<sub>off</sub> of &gt; 4x10<sup>4</sup> with ...


High field transport properties of 2D and nanoribbon graphene FETs

2009 Device Research Conference, 2009

In the past we were able to drive back-gated 2D graphene transistors to saturation regime. Now we present the realization of these properties in double-gated graphene nanoribbon field effect transistors (GNR FETs). We were able to achieve I<sub>on</sub>/I<sub>off</sub> ratio of 10<sup>3</sup> using either top or back-gates and we analyzed the high field characteristics of such devices.


Power integrated circuits-progress, prospects and challenges

IEEE Transactions on Electron Devices, 1989

PICs (power integrated circuits) are defined as ICs combining high-voltage and/or high-current components monolithically with low-voltage/low-current control components. Broadly, three classes of technologies, based on the techniques for isolating the high- and low-voltage components, have been developed for PICs: junction-isolated, self-isolated and dielectrically isolated. Each of these technologies has found its way into applications that result in optimal performance per ...


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Educational Resources on Double-gate FETs

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IEEE.tv Videos

BSIM Spice Model Enables FinFET and UTB IC Design
IMS 2011 Microapps - Tools for Creating FET and MMIC Thermal Profiles
Double Barrier Memristive Devices for Neuromorphic Computing - Martin Zeigler: 2016 International Conference on Rebooting Computing
Kaizad Mistry of Intel accepts the IEEE Corporate Innovation Award - Honors Ceremony 2016
Steep Slope Devices: Advanced Nanodevices - Nicolo Oliva at INC 2019
Abbas El Gamal accepts the IEEE Richard W. Hamming Medal - Honors Ceremony 2016
RF-pFET in Fully Depleted SOI Demonstrates 420GHz FT: RFIC Industry Showcase 2017
William S. Carter and Stephen Trimberger - 2018 Donald O. Pederson Award in Solid-State Circuits at IEEE ISSCC
AM37x Sitara EVM Demonstration
Jonathan Chew & Leo Szeto Keynote - IEEE Rising Stars 2020
Quantum Computation - ASC-2014 Plenary series - 4 of 13 - Tuesday 2014/8/12
Electronic Systems for Quantum Computation - David DiVincenzo: 2016 International Conference on Rebooting Computing
A 40GHz PLL with -92.5dBc/Hz In-Band Phase Noise and 104fs-RMS-Jitter: RFIC Interactive Forum 2017
EPICS In IEEE Spotlight - NJIT 2016 Project
Multi-Level Optimization for Large Fan-In Optical Logic Circuits - Takumi Egawa - ICRC 2018
The Prospects for Scalable Quantum Computing with Superconducting Circuits - Applied Superconductivity Conference 2018
IEEE PELS Webinar Series-Galvanic Isolation for Power Supply Applications
Noise-Shaped Active SAR Analog-to-Digital Converter - IEEE Circuits and Systems Society (CAS) Distinguished Lecture
Erasing Logic-Memory Boundaries in Superconductor Electronics - Vasili Semenov: 2016 International Conference on Rebooting Computing

IEEE-USA E-Books

  • Reliability of 4H-SiC DMOSFETs Evaluated by Bias Stressing

    In this work, the threshold voltage (V<sub>TH</sub>) of n-channel 4H-SiC double-implanted metal-oxide- semiconductor field effect transistors (DMOSFETs) was measured after different gate-bias-stress durations to determine if the bias-stress induces a shift in the V<sub>TH</sub>.

  • Ballistic FET modeling using QDAME: quantum device analysis by modal evaluation

    We present an algorithm for self-consistent solution of the Poisson and Schrodinger equations in two spatial dimensions with open-boundary conditions to permit current flow. The algorithm works by discretely sampling a device's density of states using standing wave boundary conditions, decomposing the standing waves into traveling waves injected from the contacts to assign occupancies, and iterating the quantum charge with the potential to self- consistency using a novel hybrid Newton-Broyden method. A double-gate FET is simulated as an example, with applications focused on surface roughness and contact geometry.

  • Compound Semiconductor as CMOS Channel Material: Déjà vu or New Paradigm?

    We have examined the potential of double gate (DG) inter-band tunnel FETs (TFET) in 3 different material systems, Si, Ge and InAs, for logic circuit applications down to 0.25 V supply voltage (V<sub>CC</sub>). Based on the two- dimensional numerical drift-diffusion simulations, we conclude that 30 nm gate length InAs (indium arsenide) based TFETs can achieve I<sub>on</sub>/I<sub>off</sub> of &gt; 4x10<sup>4</sup> with &lt; 1 ps intrinsic delay at 0.25 V V<sub>CC</sub>. In fact, the InAs TFETs show the maximum benefit when their supply voltage V<sub>CC</sub> is scaled aggressively down to 0.25 V and this benefit primarily arises from a) efficient tunneling under low electric field and b) their higher source-side injection velocity. MOSFETs or quantum-well FETs in this low V<sub>DD</sub> range do not even meet the I<sub>on</sub>-I<sub>off</sub> stipulation of 10<sup>4</sup>.

  • High field transport properties of 2D and nanoribbon graphene FETs

    In the past we were able to drive back-gated 2D graphene transistors to saturation regime. Now we present the realization of these properties in double-gated graphene nanoribbon field effect transistors (GNR FETs). We were able to achieve I<sub>on</sub>/I<sub>off</sub> ratio of 10<sup>3</sup> using either top or back-gates and we analyzed the high field characteristics of such devices.

  • Power integrated circuits-progress, prospects and challenges

    PICs (power integrated circuits) are defined as ICs combining high-voltage and/or high-current components monolithically with low-voltage/low-current control components. Broadly, three classes of technologies, based on the techniques for isolating the high- and low-voltage components, have been developed for PICs: junction-isolated, self-isolated and dielectrically isolated. Each of these technologies has found its way into applications that result in optimal performance per unit cost. Simultaneously with the development of technologies, several advancements have been made in high- voltage/power devices suitable for integration. These included the reduced surface field lateral double diffused MOS transistor (RESURF LDMOS), the isolated vertical DMOS (VDMOS), the lateral insulated gate bipolar transistor (LIGBT), the high-voltage RESURF bipolar transistors, the Schottky injection FET (SINFET), and the trench sidewall channel DMOS (TDMOS). Innovative device designs like the LIGBT have resulted in die sizes reduced by a factor of 3 to 5 and therefore in lower cost. In high-current applications, trench-based power devices are being developed for silicon die size reduction by more than a factor of 2. Additionally, with high-density control sections and cell- library-based automated design methods, custom ASIC (application-specific IC) designs are being developed rapidly at lower cost.

  • Trench gate integration into planar technology for reduced on-resistance in LDMOS devices

    In this paper, we report on the reduction of device resistance by up to 49% in junction isolated lateral double diffused metal-oxide-semiconductor (LDMOS) field effect transistors by incorporating trench gates into conventional planar technology. The process and device simulations of this novel device topology are based on different state-of-the-art LDMOS field effect transistor concepts with and without a reduced surface field extension (buried p-well) for high voltage applications used for standard IC and ASIC manufacturing processes in commercially available foundry processes. A limited number of additional process steps are required for manufacturing such a device, and the well implants can remain unchanged. By a straight-forward combination of trench gate with planar gate topology the device resistance can be reduced from 217mΩ·mm2down to 110mΩ·mm2for an underlying 50V LDMOS device with a 3.3V gate oxide. The robustness of trench gate integration into existing planar gate technology is demonstrated by fully maintaining the specified blocking properties.

  • Band to Band Tunneling Study in High Mobility Materials : III-V, Si, Ge and strained SiGe

    Based on the complex bandstructure obtained by local empirical pseudopotential method (LEPM), we have developed a band to band tunneling model (BTBT), which captures band structure information, all possible transitions between different valleys, energy quantization and quantized density of states. Theoretical model is verified by experimental study on tunnel diodes on various semiconductors. BTBT leakage current in high mobility (mu) channel double gate FET is studied. We have shown that quantum confinement effect in DGFET can suppress BTBT leakage current.

  • Comparative Study of Si, Ge and InAs based Steep SubThreshold Slope Tunnel Transistors for 0.25V Supply Voltage Logic Applications

    This paper examines the potential of double gate (DG) inter-band tunnel FETs (TFET) in 3 different material systems, Si, Ge and InAs, for logic circuit applications down to 0.25 V supply voltage (V&lt;sub&gt;CC&lt;/sub&gt;). Based on two-dimensional numerical drift-diffusion simulations, we show that 30 nm gate length (LG) InAs (indium arsenide) based TFETs can achieve I&lt;sub&gt;on&lt;/sub&gt;/I&lt;sub&gt;off&lt;/sub&gt; of &gt;4x10&lt;sup&gt;4&lt;/sup&gt; with &lt;1 ps intrinsic delay at 0.25 V V&lt;sub&gt;CC&lt;/sub&gt;. The key features of the InAs TFETs are: (a) asymmetric source drain design to suppress the ambipolar leakage (b) use of a lower dielectric constant gate oxide (non high-K) and (c) high source side injection velocity at moderate electric fields. Thus, narrow bandgap semiconductor based DG TFETs provide a promising device option for ultra-low standby and dynamic power high-speed logic circuits operating under quarter volt supply voltages.

  • Circuit Design with Independent Double Gate Transistors

    Circuits with transistors using independently controlled gates have been designed to reduce the number of transistors and to increase the logic density per area. This paper proposed a full adder and substractor circuit with novel Vertical Slit Field Effect Transistor and unique independent double gate properties to demonstrate the possible advantages for independent double gate circuits. With the help of double gate transistor, some of the used parameters value has been varied significantly thus improving its performance quality. Double gate transistor circuit is the first choice for low power application domain as well as used in Radio Frequency (RF) devices.

  • Correlation between plasmon absorption and terahertz photoconductance in a grid-gated double-quantum well FET

    We refine the determination of the equilibrium density distribution in a grid- gated double-quantum-well FET, taking account of screening in the system using the Poisson equation. This calculation provides requisite input information needed for the analysis of plasmon-mediated photoconductivity resonances observed in the recent experiments of Peralta and Allen. We show that the heights of the terahertz photoconductance peaks correlate with resonant terahertz plasmon absorbance.



Standards related to Double-gate FETs

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Jobs related to Double-gate FETs

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