Conferences related to Digital-controlled oscillators

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2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe)

Energy conversion and conditioning technologies, power electronics, adjustable speed drives and their applications, power electronics for smarter grid, energy efficiency,technologies for sustainable energy systems, converters and power supplies


2020 59th IEEE Conference on Decision and Control (CDC)

The CDC is the premier conference dedicated to the advancement of the theory and practice of systems and control. The CDC annually brings together an international community of researchers and practitioners in the field of automatic control to discuss new research results, perspectives on future developments, and innovative applications relevant to decision making, automatic control, and related areas.


2020 IEEE 29th International Symposium on Industrial Electronics (ISIE)

ISIE focuses on advancements in knowledge, new methods, and technologies relevant to industrial electronics, along with their applications and future developments.


2020 IEEE Industry Applications Society Annual Meeting

The Annual Meeting is a gathering of experts who work and conduct research in the industrial applications of electrical systems.


2020 IEEE International Conference on Consumer Electronics (ICCE)

The International Conference on Consumer Electronics (ICCE) is soliciting technical papersfor oral and poster presentation at ICCE 2018. ICCE has a strong conference history coupledwith a tradition of attracting leading authors and delegates from around the world.Papers reporting new developments in all areas of consumer electronics are invited. Topics around the major theme will be the content ofspecial sessions and tutorials.


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Periodicals related to Digital-controlled oscillators

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Biomedical Engineering, IEEE Transactions on

Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Consumer Electronics, IEEE Transactions on

The design and manufacture of consumer electronics products, components, and related activities, particularly those used for entertainment, leisure, and educational purposes


Control Systems Technology, IEEE Transactions on

Serves as a compendium for papers on the technological advances in control engineering and as an archival publication which will bridge the gap between theory and practice. Papers will highlight the latest knowledge, exploratory developments, and practical applications in all aspects of the technology needed to implement control systems from analysis and design through simulation and hardware.


Fuzzy Systems, IEEE Transactions on

Theory and application of fuzzy systems with emphasis on engineering systems and scientific applications. (6) (IEEE Guide for Authors) Representative applications areas include:fuzzy estimation, prediction and control; approximate reasoning; intelligent systems design; machine learning; image processing and machine vision;pattern recognition, fuzzy neurocomputing; electronic and photonic implementation; medical computing applications; robotics and motion control; constraint propagation and optimization; civil, chemical and ...


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Most published Xplore authors for Digital-controlled oscillators

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Xplore Articles related to Digital-controlled oscillators

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A simple CMOS digital controlled oscillator with high resolution and linearity

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187), 1998

This paper presents a new DCO (digital controlled oscillator) circuit which has a very simple structure with high resolution and linearity. For example, a six bit DCO only requires seventeen MOS transistors. As a result of the simple structure, the new DCO also consumes less power compared to other DCO designs. Another added feature of this new design is that ...


An on-chip automatic tuning circuit with VCO for multi-bit A/D-D/A calibration

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360), 1999

In this paper we introduce an on-chip automatic tuning circuit using a proposed voltage-controlled oscillator. The prepared on-chip automatic tuning circuit is designed in a 0.65 /spl mu/m 3.3 V CMOS process for tuning of the passive component variation. This tuning circuit could reduce the large differences between code values and real output values, however, the dual slope tuning circuit ...


Full digital dimming regulation of fluorescent lamps with -54 dB/Hz light ripple

Fourtieth IAS Annual Meeting. Conference Record of the 2005 Industry Applications Conference, 2005., 2005

The digital regulation principle for electronic ballasts for flourescent lamps presented here is well suited for system-on-chip integration of digital controlled ballasts for dimming applications. The digital regulation achieves a 16-bit adjustment accuracy of the lamp voltage frequency from 40 kHz to 120 kHz using only a 40 MHz system clock. A digital second order /spl Delta//spl Sigma/-modulator converts the ...


Digital Controlled Oscillator

ESSCIRC '88: Fourteenth European Solid-State Circuits Conference, 1988

A monolithically integrated, digitally controlled oscillator is presented. It has an output frequency range from 18.9 Hz to ≫ 20 MHz, the long term stability of a quartz oscillator and a short term clock edge uncertainty with a standard deviation of 0.4 ns. The digital frequency control is fully linear with a resolution of 18.9 Hz. The only required external ...


Sampling and quantizing noise minimization of a digital phase locked loop

Proceedings of the IEEE, 1978

In this note a new technique of minimizing the sampling and quantizing jitter of a digital phase locked loop has been suggested. Also presented are the experimental results in support of the conclusions.


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Educational Resources on Digital-controlled oscillators

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IEEE-USA E-Books

  • A simple CMOS digital controlled oscillator with high resolution and linearity

    This paper presents a new DCO (digital controlled oscillator) circuit which has a very simple structure with high resolution and linearity. For example, a six bit DCO only requires seventeen MOS transistors. As a result of the simple structure, the new DCO also consumes less power compared to other DCO designs. Another added feature of this new design is that the output signal can be phase-locked to an external input signal. A four bit DCO test circuit was fabricated with a 0.7 /spl mu/m CMOS technology. The test circuit has a die size of 0.024 mm/sup 2/ and an operating frequency range from 13 MHz to 50 MHz.

  • An on-chip automatic tuning circuit with VCO for multi-bit A/D-D/A calibration

    In this paper we introduce an on-chip automatic tuning circuit using a proposed voltage-controlled oscillator. The prepared on-chip automatic tuning circuit is designed in a 0.65 /spl mu/m 3.3 V CMOS process for tuning of the passive component variation. This tuning circuit could reduce the large differences between code values and real output values, however, the dual slope tuning circuit cannot reduce them. Also it also does not generate signal modulation because the tuning codes are fixed in the normal operation The proposed on-chip automatic tuning circuit could increase the accuracy of the passive component and reduce the complexity of the tuning circuit. Since the proposed on-chip automatic tuning circuit operates at several hundreds MHz speed, it can be applied to real time operation especially a calibration circuit for a high speed A/D converter. It may be able to compensate for the variation of passive components within a maximum range of /spl plusmn/1.0% at /spl plusmn/56% RC time constant variation of the detecting integrator.

  • Full digital dimming regulation of fluorescent lamps with -54 dB/Hz light ripple

    The digital regulation principle for electronic ballasts for flourescent lamps presented here is well suited for system-on-chip integration of digital controlled ballasts for dimming applications. The digital regulation achieves a 16-bit adjustment accuracy of the lamp voltage frequency from 40 kHz to 120 kHz using only a 40 MHz system clock. A digital second order /spl Delta//spl Sigma/-modulator converts the 16-bit target value for the lamp frequency to a 10-bit value for the digital controlled oscillator that has a time resolution of 25 nsec. The virtual enhancement of the time resolution of the DCO allows a fine adjustment of the average lamp frequency making an analog VCO unnecessary. The principle is well suited for dimming of compact fluorescent lamps down to 1% dim level with a very low light flicker of -54 dB equivalent to 56 /spl mu/W/Hz in the visible frequency range.

  • Digital Controlled Oscillator

    A monolithically integrated, digitally controlled oscillator is presented. It has an output frequency range from 18.9 Hz to ≫ 20 MHz, the long term stability of a quartz oscillator and a short term clock edge uncertainty with a standard deviation of 0.4 ns. The digital frequency control is fully linear with a resolution of 18.9 Hz. The only required external component is a reference quartz. The circuit operates from a single 5 V power supply and is fabricated in a 1.5 μm, double metal, single poly, CMOS process. The chip area is 4.1 mm2.

  • Sampling and quantizing noise minimization of a digital phase locked loop

    In this note a new technique of minimizing the sampling and quantizing jitter of a digital phase locked loop has been suggested. Also presented are the experimental results in support of the conclusions.

  • A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency

    In this paper a new architecture for all digital phase locked loop (ADPLL) is proposed The new architecture is based on the ADPLL architecture proposed by Motorola in 1995 but modified in some block A new binary search decision scheme was used to accelerate the frequency acquisition process. It can reduce the chip area and increase the operating frequency. In this design, a 14-bit control word is used to control the digital control oscillator. The new type ADPLL has been designed and implemented by TSMC's 0-35 /spl mu/ IP4M CMOS process for 3.3V applications. The phase lock process takes 20-reference cycle, and the maximum frequency of the proposed ADPLL is about 820MHz.

  • A 3.3 GHz LC-based digitally controlled oscillator with 5kHz frequency resolution

    This paper reports a LC-based digitally controlled oscillator (DCO) with an enhanced frequency resolution and an extended linear frequency tuning range. It has a center frequency of 3.3 GHz. and a frequency tuning range of 600 MHz covered by 64 different frequency bands. Each frequency band has 2048 linear tuning levels with a frequency step of 5 kHz. This DCO was implemented in 90 nm CMOS and the measured frequency tuning characteristics arc provided in this paper. The DCO exhibits a phase noise of -11 NdBc/Hz. at 1 MHz frequency offset. The DCO core consumes 2 mA current from 1.2 V supply.

  • A digitally controlled 2.4-GHz oscillator in 65-nm CMOS

    This paper presents a 2.4-GHz digitally controlled oscillator (DCO). The circuit is designed using a 65-nm six-metal CMOS technology with an operating voltage of 1.2 V. The DCO comprises an LC oscillator core and the digital interface logic. It has a frequency range of about 200 MHz covering the 2.4-GHz ISM band, with around 5 MHz available for frequency modulation. Its frequency quantization step is approximately 20 kHz, with a digital SigmaDelta-modulator used to allow a 5-bit fractional digital control and provide an effective frequency resolution better than 1 kHz. Its free running oscillation phase noise is -125 dBc/Hz at 1 MHz frequency offset with 4.8 mA biasing current. The power consumption is adjustable from 1.8 mW to 12 mW.

  • Direct mounting of quartz crystal on a CMOS PLL chip

    This paper reports progress on directly mounting a quartz crystal on a CMOS oscillator and PLL chip. This approach minimizes the distance between the quartz crystal resonator and the oscillator circuitry and can allow reduced power with reduced stray coupling effects. This approach also allows simplified packaging and can reduce the volume and weight of precision oscillators.

  • An All-Digital PLL for Video Pixel Clock Regeneration Applications

    This paper presents an all-digital PLL (ADPLL) for the pixel clock regeneration in analog video signal digitization applications. A fine frequency resolution, 1-1-1 MASH structure based fractional-N PLL (FN-PLL) is used as the digital-controlled oscillator (DCO). Two loop filters which are triggered by different clock frequencies and both with adaptive gain controllers are combined together working at different states to increase both the tracking speed and the locked jitter performance. The ADPLL maximum output frequency is determined by the FN-PLL's voltage-controlled oscillator (VCO) which can be upper than lGhz. It covers any VESA and HDTV specification requirements even at 4X over-sampling ratio. A test chip contains this ADPLL prototype has been implemented in a 0.13 um CMOS technology. The layout area is about 0.2 mm<sup>2</sup> , the measured RMS jitter is 32.4 ps.



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