Conferences related to Digital integrated circuits

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2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe)

Energy conversion and conditioning technologies, power electronics, adjustable speed drives and their applications, power electronics for smarter grid, energy efficiency,technologies for sustainable energy systems, converters and power supplies


2020 IEEE Frontiers in Education Conference (FIE)

The Frontiers in Education (FIE) Conference is a major international conference focusing on educational innovations and research in engineering and computing education. FIE 2019 continues a long tradition of disseminating results in engineering and computing education. It is an ideal forum for sharing ideas, learning about developments and interacting with colleagues inthese fields.


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


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Periodicals related to Digital integrated circuits

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Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


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Most published Xplore authors for Digital integrated circuits

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Xplore Articles related to Digital integrated circuits

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IC design for a digital wireless endoscope capsule system

2004 Asia-Pacific Radio Science Conference, 2004. Proceedings., 2004

The requirement of an IC for a biomedical application is introduced. An analog-digital mixed-mode IC for a digital wireless endoscope capsule is designed using the CMOS process. The presented system has some characterized features, such as real time endoscopy image monitoring, adjustment of the view angle and focus, 3-dimensional range image acquisition, and controllability of capsule movement. The architecture, specification ...


Substrate noise measurement by using noise-selective voltage comparators in analog and digital mixed-signal integrated circuits

IEEE Transactions on Instrumentation and Measurement, 1999

In mixed-signal integrated circuits (IC's), substrate noise produced by high- speed digital circuits passes to the on-chip analog circuits through the substrate and seriously degrades their performance. We have developed a method for measuring the substrate noise by using noise-selective chopper-type voltage comparators as noise detectors. This method can detect the wide-band substrate noise so we can analyze and further ...


0.5-/spl mu/m CMOS circuits for demodulation and decoding of an OFDM-based digital TV signal conforming to the European DVB-T standard

IEEE Journal of Solid-State Circuits, 1998

In the context of digital terrestrial TV based on the DVB-T standard, four 0.5-/spl mu/m CMOS IC's (IC1-IC4) are presented. IC1 integrates an 8-K fast Fourier transform for orthogonal frequency division multiplexing demodulation, IC2 performs channel estimation/correction, and IC3 is a forward error corrector implementing a Viterbi and a Reed-Solomon decoder. IC4, which is based on a digital signal-processing core, ...


Design-for-Test of Mixed-Signal Integrated Circuits

2006 49th IEEE International Midwest Symposium on Circuits and Systems, 2006

What to test and what does test need for a complex mixed-signal ASIC are the two main issues this tutorial will try to focus. It will account for several factors: Stimuli generation. An efficient test procedure would use a single signal especially a signal that is easily supplied to a selected input or generated on-chip. Sufficient access. It is preferable ...


Design-for-Test of Mixed-Signal Integrated Circuits

2006 49th IEEE International Midwest Symposium on Circuits and Systems, 2006

What to test and what does test need for a complex mixed-signal ASIC are the two main issues this tutorial will try to focus. It will account for several factors: Stimuli generation. An efficient test procedure would use a single signal especially a signal that is easily supplied to a selected input or generated on-chip. Sufficient access. It is preferable ...


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Educational Resources on Digital integrated circuits

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IEEE-USA E-Books

  • IC design for a digital wireless endoscope capsule system

    The requirement of an IC for a biomedical application is introduced. An analog-digital mixed-mode IC for a digital wireless endoscope capsule is designed using the CMOS process. The presented system has some characterized features, such as real time endoscopy image monitoring, adjustment of the view angle and focus, 3-dimensional range image acquisition, and controllability of capsule movement. The architecture, specification and characteristics of the IC are demonstrated.

  • Substrate noise measurement by using noise-selective voltage comparators in analog and digital mixed-signal integrated circuits

    In mixed-signal integrated circuits (IC's), substrate noise produced by high- speed digital circuits passes to the on-chip analog circuits through the substrate and seriously degrades their performance. We have developed a method for measuring the substrate noise by using noise-selective chopper-type voltage comparators as noise detectors. This method can detect the wide-band substrate noise so we can analyze and further reduce its effect. A switched capacitance is selectively loaded on the output of the inverter amplifier of the comparator during the comparison period in order to reduce the noise detected at the transition from compare to auto-zero. In contrast, the noise at the transition from auto-zero to compare can be selectively detected. Waveforms of high-frequency substrate noise were reconstructed by using this on-chip-noise detector incorporating the noise-selective comparators implemented using a 0.5-/spl mu/m CMOS bulk process.

  • 0.5-/spl mu/m CMOS circuits for demodulation and decoding of an OFDM-based digital TV signal conforming to the European DVB-T standard

    In the context of digital terrestrial TV based on the DVB-T standard, four 0.5-/spl mu/m CMOS IC's (IC1-IC4) are presented. IC1 integrates an 8-K fast Fourier transform for orthogonal frequency division multiplexing demodulation, IC2 performs channel estimation/correction, and IC3 is a forward error corrector implementing a Viterbi and a Reed-Solomon decoder. IC4, which is based on a digital signal-processing core, performs the synchronization tasks of the complete receiver. These four chips have been designed and manufactured using a 0.5-/spl mu/m, 3,3-V, triple-metal CMOS process. Their global complexity is about 500 kgates of standard cells and 1.5 Mbits of memory, which represents a total die area of 435 mm/sup 2/ in 0.5 /spl mu/m. The total power dissipation is about 3.5 W when working at nominal frequency. More generally, these four IC's constitute the digital front-end part of a global chipset receiver (specified within the European project DVBird), also including an analog front end and a MPEG2 demultiplexer IC.

  • Design-for-Test of Mixed-Signal Integrated Circuits

    What to test and what does test need for a complex mixed-signal ASIC are the two main issues this tutorial will try to focus. It will account for several factors: Stimuli generation. An efficient test procedure would use a single signal especially a signal that is easily supplied to a selected input or generated on-chip. Sufficient access. It is preferable to have access to several internal nodes that the tester can read either sequentially or in parallel. Such access permits selection of convenient test points. Single test output. The output should contain all the information required to interpret test signals. Having the information digitally encoded would also reduce tester requirements. Simple measurement set. This set must contain sufficient information about the circuit under test's operational status. System-level decomposition. An efficient test procedure will employ a system-level strategy for decomposing the ASIC into meaningful parts. This decomposition permits testing of each part using a common procedure. These issues are worth attention for specific circuit classes, since there is no universal method valid for any kind of analog and/or mixed-signal function. These factors and their application for solving testing problems in general or for specific circuits will be presented and discussed. In particular, during the presentations making part of this tutorial, more attention will be paid to integrated filters (Switched-Capacitor and continuous-time), integrated A/D and D/A converters, and PLLs.

  • Design-for-Test of Mixed-Signal Integrated Circuits

    What to test and what does test need for a complex mixed-signal ASIC are the two main issues this tutorial will try to focus. It will account for several factors: Stimuli generation. An efficient test procedure would use a single signal especially a signal that is easily supplied to a selected input or generated on-chip. Sufficient access. It is preferable to have access to several internal nodes that the tester can read either sequentially or in parallel. Such access permits selection of convenient test points. Single test output. The output should contain all the information required to interpret test signals. Having the information digitally encoded would also reduce tester requirements. Simple measurement set. This set must contain sufficient information about the circuit under test's operational status. System-level decomposition. An efficient test procedure will employ a system-level strategy for decomposing the ASIC into meaningful parts. This decomposition permits testing of each part using a common procedure. These issues are worth attention for specific circuit classes, since there is no universal method valid for any kind of analog and/or mixed-signal function. These factors and their application for solving testing problems in general or for specific circuits will be presented and discussed. In particular, during the presentations making part of this tutorial, more attention will be paid to integrated filters (Switched-Capacitor and continuous-time), integrated A/D and D/A converters, and PLLs.

  • A 25 Ms/s 8-b-10 Ms/s 10-b CMOS data acquisition IC for digital storage oscilloscopes

    A data acquisition IC has been developed for digital storage oscilloscopes (DSOs). The entire DSO front-end except an input attenuator was integrated using 1-/spl mu/m double-poly, double-metal (DPDM) CMOS process technology. In the analog-to-digital conversion, a time-interleaved successive approximation architecture effectively enables both 25 Ms/s 8-b and 10 Ms/s 10-b operation. The input signal conditioner consists of a variable gain amplifier (VGA) and a second-order programmable low-pass filter (LPF) using folded-cascode structures with current feedback circuits. The overall gain is externally controllable from 12 dB to 38 dB, and the bandwidth is programmable at 500 kHz, 5 MHz, and 25 MHz. The chip consumes 340 mW at the 25 Ms/s operating condition and less than 8 mW in the power-down mode from a single 5 V supply.

  • An integrated /spl pi//4-shift QPSK baseband modulator

    A mixed analog-digital /spl pi//4 shift QPSK modulator IC targeting the Japanese digital personal handy phone system is reported. The chip includes modulator, root-Nyquist FIR, D/A converter and smoothing filter functions. The 13.5 mm/sup 2/ IC was fabricated in 1.2 /spl mu/m CMOS. It consumes 21 mW and operates from 3 V or 5 V supplies.<<ETX>>

  • The dual origins of a bipolar breakthrough (I/sup 2/L)

    The author describes the independent discovery of integrated injection logic (I/sup 2/L) in the early 1970s by researchers at IBM in West Germany and at Philips in the Netherlands. He examines the factors that motivated the work and contrasts the viewpoints and working methods of the two teams, the Germans proceeding along a logical path to a solution that revealed itself to the Dutch team in a flash of intuition.<<ETX>>

  • IEE Colloquium on 'Linear Analogue Circuits and Systems' (Digest No.158)

    None

  • An analog CMOS IC for template matching

    A 3 V 0.5 /spl mu/m CMOS analog IC correlates each 9/spl times/9 pixel window in an input image with 8 stored 9/spl times/9 templates at rates up to 5 MHz and outputs the best match. Core multiply-accumulators (MACs) use 5 pJ/multiply at 320/spl times/10/sup 6/ MAC/s for a 10/spl times/ energy improvement over digital ASIC MACs and 10/spl times/ over a general DSP. The overall IC performs data sequencing, 3.6/spl times/10/sup 9/ MAC/s, and max- finding, with 8 mV resolution, while consuming 420 mW.



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