Conferences related to Decision feedback equalizers

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ICC 2021 - IEEE International Conference on Communications

IEEE ICC is one of the two flagship IEEE conferences in the field of communications; Montreal is to host this conference in 2021. Each annual IEEE ICC conference typically attracts approximately 1,500-2,000 attendees, and will present over 1,000 research works over its duration. As well as being an opportunity to share pioneering research ideas and developments, the conference is also an excellent networking and publicity event, giving the opportunity for businesses and clients to link together, and presenting the scope for companies to publicize themselves and their products among the leaders of communications industries from all over the world.


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 59th IEEE Conference on Decision and Control (CDC)

The CDC is the premier conference dedicated to the advancement of the theory and practice of systems and control. The CDC annually brings together an international community of researchers and practitioners in the field of automatic control to discuss new research results, perspectives on future developments, and innovative applications relevant to decision making, automatic control, and related areas.


2020 IEEE International Conference on Consumer Electronics (ICCE)

The International Conference on Consumer Electronics (ICCE) is soliciting technical papersfor oral and poster presentation at ICCE 2018. ICCE has a strong conference history coupledwith a tradition of attracting leading authors and delegates from around the world.Papers reporting new developments in all areas of consumer electronics are invited. Topics around the major theme will be the content ofspecial sessions and tutorials.


2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


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Periodicals related to Decision feedback equalizers

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Broadcasting, IEEE Transactions on

Broadcast technology, including devices, equipment, techniques, and systems related to broadcast technology, including the production, distribution, transmission, and propagation aspects.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Communications Letters, IEEE

Covers topics in the scope of IEEE Transactions on Communications but in the form of very brief publication (maximum of 6column lengths, including all diagrams and tables.)


Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...


Consumer Electronics, IEEE Transactions on

The design and manufacture of consumer electronics products, components, and related activities, particularly those used for entertainment, leisure, and educational purposes


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Most published Xplore authors for Decision feedback equalizers

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Xplore Articles related to Decision feedback equalizers

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Maximum SNR Transmit Filtering for Decision-Feedback Equalization in Physical Layer Network Coding

SCC 2013; 9th International ITG Conference on Systems, Communication and Coding, 2013

We consider a two-way relaying system employing physical layer network coding (PNC) in channels suffering from frequency-selective fading. In order to mitigate the distortions introduced by the channel, decision-feedback equalization (DFE) is used at the relay node. We introduce transmit filters that generate identical overall channel impulse responses for the links from both source nodes to the relay node, while ...


Multicarrier transmission

IET Signal Processing, 2008

Multicarrier transmission has recently become popular, particularly in the area of wireless broadband access technology. This tutorial overview paper formulates multicarrier transmission from a signal processing point of view and provides an in-depth analytical understanding of its constituent fundamental concepts. Multicarrier transmission and reception principles are first derived for the single transmitting antenna and single receiving antenna systems and then ...


A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS

IEEE Journal of Solid-State Circuits, 2017

This paper presents a referenceless baud-rate clock and data recovery (CDR) incorporated with a continuous-time linear equalizer (CTLE) and one-tap decision feedback equalizer (DFE) to achieve data rates from 22.5 to 32 Gb/s across a channel with Nyquist loss ranging from 10.1 to 14.8 dB. The referenceless CDR includes a proposed frequency acquisition scheme that consists of two parts: frequency ...


Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology

IEEE Journal of Solid-State Circuits, 2017

Design techniques for a complete 60-Gb/s non-return-to-zero transceiver with adaptive equalization as well as baud-rate clock and data recovery (CDR) are demonstrated. A complete equalization front end with per-path adaptation and per-sampler offset calibration enables 60-Gb/s operation over realistic channels. Current integration in the front end for energy-efficient equalization is combined with integration phase dithering to realize a robust baud-rate ...


MMSE equalizers for multitone systems without guard time

1996 8th European Signal Processing Conference (EUSIPCO 1996), 1996

Recently the concept of multitone modulation or OFDM has received much attention. For such a modulation, the dispersiveness of the channel is classically solved by the technique of guard time. In the present paper we investigate the performance of OFDM without guard time but with MIMO equalization. Linear and decision-feedback structures structures are derived for an MMSE criterion and their ...


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Educational Resources on Decision feedback equalizers

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IEEE.tv Videos

Multi-Standard 5Gbps to 28.2Gbps Adaptive, Single Voltage SerDes Transceiver with Analog FIR and 2-Tap Unrolled DFE in 28nm CMOS: RFIC Interactive Forum 2017
An Introduction to Computational Intelligence in Multi-Criteria Decision-Making: The Intersection of Search, Preference Tradeoff
Bayesian Perception & Decision from Theory to Real World Applications
Fuzzy and Soft Methods for Multi-Criteria Decision Making - Ronald R Yager - WCCI 2016
Algorithmic Decision Making: Impacts and Implications - IEEE Internet Initiative Webinar
Joint TX and Feedback RX IQ Mismatch Compensation for Integrated Direct Conversion Transmitters: RFIC Interactive Forum 2017
IEEE N3XT @ SXSW 2016: Chris Campbell, ReviewTrackers
The IEEE in 2030: 11 May 2016
Robotics History: Narratives and Networks Oral Histories: Richard Murray
WIE: Our Own Voices - Noel Schulz, Kansas State University
Recurrent Neural Networks for System Identification, Forecasting and Control
Review of Key Issues - ETAP Forum Tel Aviv 2016
Mapping Human to Robot Motion with Functional Anthropomorphism for Teleoperation and Telemanipulation with Robot Arm Hand Systems
Social Implications: Perils & Promises of AI - IEEE AI & Ethics Summit 2016
Giving Small Robots New Ways to Move
Classifying attention in Pivotal Response Treatment Videos - Corey Heath - LPIRC 2018
IEEE Authoring Parts 1 and 2: Publishing Choices
Robotics History: Narratives and Networks Oral Histories: Max Mintz
A Damping Pulse Generator Based on Regenerated Trigger Switch: RFIC Interactive Forum
Robotics History: Narratives and Networks Oral Histories: Allison Okamura

IEEE-USA E-Books

  • Maximum SNR Transmit Filtering for Decision-Feedback Equalization in Physical Layer Network Coding

    We consider a two-way relaying system employing physical layer network coding (PNC) in channels suffering from frequency-selective fading. In order to mitigate the distortions introduced by the channel, decision-feedback equalization (DFE) is used at the relay node. We introduce transmit filters that generate identical overall channel impulse responses for the links from both source nodes to the relay node, while achieving the maximum signal-to- noise ratio (SNR) for zero-forcing DFE and minimum mean-squared error DFE at the relay node. The performance gain of our novel approach is compared against a benchmark filtering scheme which also creates identical channel impulse responses to enable decision-feedback equalization at the relay.

  • Multicarrier transmission

    Multicarrier transmission has recently become popular, particularly in the area of wireless broadband access technology. This tutorial overview paper formulates multicarrier transmission from a signal processing point of view and provides an in-depth analytical understanding of its constituent fundamental concepts. Multicarrier transmission and reception principles are first derived for the single transmitting antenna and single receiving antenna systems and then extended to support more general and modern communication systems that use multiple transmitting and multiple receiving antennas.

  • A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS

    This paper presents a referenceless baud-rate clock and data recovery (CDR) incorporated with a continuous-time linear equalizer (CTLE) and one-tap decision feedback equalizer (DFE) to achieve data rates from 22.5 to 32 Gb/s across a channel with Nyquist loss ranging from 10.1 to 14.8 dB. The referenceless CDR includes a proposed frequency acquisition scheme that consists of two parts: frequency detection and frequency correction. Frequency detection is achieved by examining rising and falling data waveforms to detect discrepancies between the data rate and the locally recovered clock frequency. Frequency correction uses digitally adjustable asymmetry of the proposed adjustable baud-rate phase detector to correct any frequency error. The receiver is implemented in the TSMC 28-nm CMOS process with an analog front end consisting of a CTLE, sampling comparators, a digitally controlled oscillator, and a digital back end consisting of synthesized digital CDR logic. The open-loop frequency detector range is measured to be 39%. The closed-loop CDR capture range is measured to be 34%, limited by test equipment. The proposed frequency acquisition scheme improves the measured CDR capture range by up to 227×. At 32 Gb/s, the entire receiver consumes 102.04 mW, achieving energy consumption below 3.19 pJ/b.

  • Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology

    Design techniques for a complete 60-Gb/s non-return-to-zero transceiver with adaptive equalization as well as baud-rate clock and data recovery (CDR) are demonstrated. A complete equalization front end with per-path adaptation and per-sampler offset calibration enables 60-Gb/s operation over realistic channels. Current integration in the front end for energy-efficient equalization is combined with integration phase dithering to realize a robust baud-rate CDR. Correlation of the adaptive error sampler output with the phase dithering sequence indicates the direction of phase offset, and the resulting baud-rate CDR saves power and complexity compared to an oversampling CDR by not requiring additional clock phases/deserializers. The proposed 65-nm CMOS transceiver operates at 60 Gb/s with an eye opening of 30% UI and consumes 288 mW while equalizing 21 dB of loss at 30 GHz over a 0.7-m Twinax cable.

  • MMSE equalizers for multitone systems without guard time

    Recently the concept of multitone modulation or OFDM has received much attention. For such a modulation, the dispersiveness of the channel is classically solved by the technique of guard time. In the present paper we investigate the performance of OFDM without guard time but with MIMO equalization. Linear and decision-feedback structures structures are derived for an MMSE criterion and their performance is assessed by means of their steady-state behavior. Symbol rate equalizers following channel matched filters are derived and investigated. It is shown that equalized OFDM outperforms OFDM with guard time.

  • Enhanced decision feedback equalization

    None

  • A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET

    A 40-56 Gb/s PAM-4 receiver with ten-tap decision-feedback equalization (DFE) targeting chip-to-module and board-to-board cable interconnects is designed in 16-nm FinFET. The design implements direct feedback of the first post-cursor (h1) DFE tap to reduce the number of slicers. The h1 feedback signals are directly tapped from the master latch output of the StrongArm-based slicers. A CMOS amplifier with delayed pre-charge release is used to boost and pre- condition the h1 feedback signals before being applied to current-mode logic tap cell for optimum DFE summer settling time. The receiver achieves less than 1E-12 PRBS31 bit error rate (BER) over a channel with 10-dB loss at 14-GHz consuming 230 mW. Fully adapted by off-chip software, the receiver performance demonstrates the effectiveness of direct h1 loop and the need for higher DFE taps to achieve a required BER over channels with reflections. Receiver performance over higher loss channels up to 23 dB and/or under emulated cross- talk noise injection cases are also presented.

  • Design and Implementation of DTV Receiver

    The principles of channel synchronization and channel estimation as well as equalization in the inner receiver for both single- and multicarrier systems are introduced in this chapter, and their applications for the DTMB system is then discussed with some examples. The algorithms for the frequency tracking stage are described and share the requirement of correct timing, which requires that the timing recovery module operate properly within a certain frequency offset range. Unlike the C-OFDM, the time-domain PN sequence instead of the frequency-domain pilot signal is utilized in the TDS-OFDM system, and the receiver can use the PN sequence for channel estimation by acquiring the time-domain impulse response of the channel first and then getting the frequency-domain response through DFT, which is described in detail in the chapter. The channel estimation and equalization methods discussed here are based on the correlation algorithm for the time-domain synchronous PN sequence.

  • A flexible near-optimum detector for V-BLAST

    V-BLAST is an important multiple input and multiple output (MIMO) space-time architecture for future high data rate wireless communication system. In this paper, a novel computation-efficient metric-guided (MG) algorithm is proposed for V-BLAST signal detection. This algorithm can achieve near maximum likelihood (ML) detection performance with tractable detection complexity which is inherently adaptive to channel signal-noise ratio (SNR). Through adjusting the value oof one parameter, MG algorith offers the flexibility of achieving any in-between performance-complexity tradeoff between an efficient near-ML detection and original nulling/cancelling algorithm for V-BLAST. Simulation results show that proposed algorithm can offer near-ML detection performance with complexity even less than that of the Schnorr-Euchner sphere decoder (M. O. Damen et al., 2003) and stack algorithm (S. Baro et al., 2003).

  • Design of multilevel decision feedback equalizers

    Multilevel decision feedback equalization scheme (MDFE) is an efficient and simple realization of the fixed-delay tree search with decision feedback (FDTS/DF) for channels using RLL(1,k) codes. In MDFE, the entire tree-search is replaced with a 2-tap transversal filter and a binary comparator with negligible loss in performance. This 2-tap filter can be combined with the forward and feedback equalizers resulting in a structure that is physically identical to DFE but requires very different equalizer settings. This paper focuses on equalizer design for MDFE. It is first shown that the MDFE scheme can also be derived without using the principle of tree-search by exploiting the run-length constraints imposed by the RLL(1,k) code in conjunction with the maximization of an appropriately defined signal-to-noise ratio (SNR). Recognizing that a multilevel eye Is formed at the comparator, we define this SNR as the eye-opening divided by noise plus intersymbol interference. This formulation directly leads to a novel adaptive scheme based on the well known LMS algorithm. The relationship between this work and the earlier derivation of MDFE is then clarified. We also develop a noniterative analytical approach for the optimum equalizer design. Because of the economy of implementation, there is particular interest in the design of continuous-time forward equalizers. A noniterative analytic design approach, which does not suffer from local minima problems, is developed for such equalizers. Computer simulation results are presented for comparing the different design approaches.



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