Conferences related to Data buses

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2020 IEEE International Symposium on Information Theory (ISIT)

Information theory, coding theory, communication theory, signal processing, and foundations of machine learning


2020 IEEE International Conference on Robotics and Automation (ICRA)

The International Conference on Robotics and Automation (ICRA) is the IEEE Robotics and Automation Society’s biggest conference and one of the leading international forums for robotics researchers to present their work.


2020 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)

The Conference focuses on all aspects of instrumentation and measurement science andtechnology research development and applications. The list of program topics includes but isnot limited to: Measurement Science & Education, Measurement Systems, Measurement DataAcquisition, Measurements of Physical Quantities, and Measurement Applications.


IGARSS 2020 - 2020 IEEE International Geoscience and Remote Sensing Symposium

All fields of satellite, airborne and ground remote sensing.


2020 IEEE Applied Power Electronics Conference and Exposition (APEC)

APEC focuses on the practical and applied aspects of the power electronics business. Not just a power designer’s conference, APEC has something of interest for anyone involved in power electronics including:- Equipment OEMs that use power supplies and converters in their equipment- Designers of power supplies, dc-dc converters, motor drives, uninterruptable power supplies, inverters and any other power electronic circuits, equipments and systems- Manufacturers and suppliers of components and assemblies used in power electronics- Manufacturing, quality and test engineers involved with power electronics equipment- Marketing, sales and anyone involved in the business of power electronic- Compliance engineers testing and qualifying power electronics equipment or equipment that uses power electronics



Periodicals related to Data buses

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Advanced Packaging, IEEE Transactions on

The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.


Aerospace and Electronic Systems Magazine, IEEE

The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.


Communications Magazine, IEEE

IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


Computer Architecture Letters

Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing



Most published Xplore authors for Data buses

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Xplore Articles related to Data buses

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A 64b floating point processor

1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1982

A floating point chip set capable of one-million scalar operations per second will be reported. The set consists of add/subtract, multiply and divide chips.


A 100ns 150mW 64Kbit ROM

1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1978

A sub 100ns 64K ROM using standard N-channel silicon-gate technology will be discussed. The ROM organized as 8K words by 8bits per word operates from a single 5V supply and has a typical access time and power of 80ns and 150mW.


Multi-inverter UPS system with redundant load sharing control

15th Annual Conference of IEEE Industrial Electronics Society, 1989

The concept of a redundant multi-inverter UPS (uninterruptible power supply) system includes extended monitoring of the status and the operating conditions of all power electronic equipment. Each block of the UPS system is monitored by two independent microcomputers that process the same data. The microcomputers are part of a redundant distributed monitoring system, being separately interlinked by two serial data ...


Respective parts of capacitive and inductive coupling

Proceedings. 9th IEEE Workshop on Signal Propagation on Interconnects, 2005., 2005

Rapid progress in integrated circuit technology has led to an increase in the switching speed of the digital chip. As a result, there is a growing interest in the inductance associated with signal lines. In this paper we show the influence of inductance on crosstalk voltage by considering a configuration of two parallel coupled interconnects. For a typical DSM (deep-sub-micron) ...


Automatic production test equipment (APTE) for the B-2

Conference Record AUTOTESTCON '91 IEEE Systems Readiness Technology Conference Improving Systems Effectiveness in the Changing Environment of the '90s, 1991

The automatic production test equipment (APTE) was developed to provide an integrated capability for seven test conductors and one chief test conductor to interactively test a system with bus architecture. Each test conductor has access to 35 data buses and a centralized database to generate stimuli and monitor responses from the vehicle subsystem. The chief test conductor resolves potential resource ...



Educational Resources on Data buses

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IEEE-USA E-Books

  • A 64b floating point processor

    A floating point chip set capable of one-million scalar operations per second will be reported. The set consists of add/subtract, multiply and divide chips.

  • A 100ns 150mW 64Kbit ROM

    A sub 100ns 64K ROM using standard N-channel silicon-gate technology will be discussed. The ROM organized as 8K words by 8bits per word operates from a single 5V supply and has a typical access time and power of 80ns and 150mW.

  • Multi-inverter UPS system with redundant load sharing control

    The concept of a redundant multi-inverter UPS (uninterruptible power supply) system includes extended monitoring of the status and the operating conditions of all power electronic equipment. Each block of the UPS system is monitored by two independent microcomputers that process the same data. The microcomputers are part of a redundant distributed monitoring system, being separately interlinked by two serial data buses through which they communicate. They establish a hierarchy among the participating blocks, defining one of the healthy inverter blocks as the master. The actual master runs the central synchronizing unit for the entire system, while the slave units perform the control of equal active and reactive load sharing. Operation and fault detection are experimentally exemplified in a dual inverter system having a rating of 10 kVA of redundant power.<<ETX>>

  • Respective parts of capacitive and inductive coupling

    Rapid progress in integrated circuit technology has led to an increase in the switching speed of the digital chip. As a result, there is a growing interest in the inductance associated with signal lines. In this paper we show the influence of inductance on crosstalk voltage by considering a configuration of two parallel coupled interconnects. For a typical DSM (deep-sub-micron) geometry structure for data buses, we show that when standard distributed RC models are used and inductive effects are ignored, large errors can occur in the prediction and evaluation of the crosstalk voltage. This is all the more important because the inductance effect will increase as technologies downscale. For our structure, the inductive part of crosstalk can reach 30% when the input transition time at the beginning of the aggressor line is 50ps. The sensibility of inductances values, including self and mutual inductances are then analysed.

  • Automatic production test equipment (APTE) for the B-2

    The automatic production test equipment (APTE) was developed to provide an integrated capability for seven test conductors and one chief test conductor to interactively test a system with bus architecture. Each test conductor has access to 35 data buses and a centralized database to generate stimuli and monitor responses from the vehicle subsystem. The chief test conductor resolves potential resource conflicts and monitors critical parameters for safety considerations. Test program development is accomplished using windows, graphics, and a menu-driven environment to eliminate the need for extensive operator training and software language skills.<<ETX>>

  • Spacelab Payloads Standard Multi-processor Computer System

    None

  • The ChipCflow: A Tool to Generate Hardware Accelerators Using a Static Dataflow Machine Designed for a FPGA

    The execution of sections of algorithms in hardware accelerators, appears as a alternative to speed up performance with low power consumption. In this article the Chip flow project is presented, the goal of Chip flow is conversion of C code in a static dataflow machine designed for a FPGA. The conversion process is discussed and some initial results are presented. The results of Chip flow are compared with a Intel core i7 processor and modern GPU. The results of benchmarks implemented show that Chip flow is a newer alternative for the development of hardware accelerators, with a good performance with low power consumption.

  • 500 Mb/s non-precharged data bus for high-speed DRAM

    For a DRAM core with bandwidth per memory more than one order of magnitude higher than the current DRAMs without increasing the number of internal busses and the area and power they require, the data rate per DRAM must be increased. This nonprecharged bus combined with a bus amplifier that employs partial response detection (PRD) achieves 500Mb/s data-bus rate for read, 2.5 times larger than that of a conventional DRAM core. The isolated sense amplifier (ISSA) realizes more than 400 Mb/s data-bus data rate for write. Due to the intrinsic high data-rate of the bus, no core interleaves and no increase in the number of buses is needed to achieve the high-core bandwidth and high-data locality.

  • A CAD methodology for the characterization of wide on-chip buses

    In this paper, we describe a CAD methodology for the full electrical characterization of high-performance, on-chip data buses. The goal of this methodology is to allow the accurate modeling and analysis of wide, on-chip data buses as early as possible in the design cycle. The modeling is based on a manufacturing (rather than design-manual) description of the back-end-of- the-line (BEOL) cross section of a given technology and on a full yet contained description of the power-ground mesh in which the data-bus is embedded. One major aspect of the resulting electrical models is that they allow the designer to evaluate the wide bus from the three viewpoints of signal timing, crosstalk (both inductive and capacitive), and common-mode signal integrity. Another major aspect is that they take into account such important high-frequency phenomena as the dependence of the current return- path resistance on frequencies. The CAD methodology described in this paper has been extensively correlated with on-chip hardware measurements.

  • The Denver transitway vehicle system - A preliminary design

    The Transitway/Mall is a major transportation project designed for the central business district of metropolitan Denver. Its goals are threefold: 1. To lessen traffic congestion in the downtown area 2. To provide more efficient bus service to city and suburban neighborhoods 3. To create a new pedestrian environment in the downtown area -- a place for people. The project will transform 16th Street between Broadway and Larimer into a tree-lined pedestrian precinct. Electric battery-powered shuttle vehicles will carry passengers to and from transportation transfer facilities located at each end. Express computer buses will enter the transfer facilities at a below-street concourse where riders will transfer to transitway vehicles waiting at ground level. Shuttles will leave the terminals every 70 seconds stopping at each block along 16th Street. By intercepting express buses at the edges of the retail-office core, there will be fewer buses on downtown streets and therefore substantially less traffic congestion. Also commuter buses will be able to get in and out of downtown much faster, enabling them to make additional productive trips during rush hour. The vehicle system is being designed to meet some unique requirements of the Denver Transitway/Mall. The preliminary vehicle system design consists of performance requirements, an operations profile, fleet sizing, maintenance program, and maintenance facility requirements, in addition to vehicle specifications. Specified features of the battery-powered vehicle include a lateral guidance system, a low floor, wide doors, a large expanse of glass, a capability of operating in tandem, and a rear-mounted dc traction motor.



Standards related to Data buses

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Guide to Specifications for Gas-Insulated, Electric Power Substation Equipment

This guide covers the technical requirements for the design, fabrication, testing, installation, and in-service performance of gas-insulated substations(GIS). In line with the user functional one-line diagram, the supplier should furnish all components of the GIS such as circuit breakers(CB), disconnect switches(DS), maintenance ground switches (MGS), fast-acting ground switches(FGS), voltage transformers(VT), current transformers(CT), SF6-to-air bushings, SF6-to-cable terminations, surge arresters, all the ...


IEEE Standard for a High-Performance Serial Bus

This standard describes a high-speed, low-cost serial bus suitable for use as a peripheral bus, a backup to parallel backplane buses, or a local area network. Highlights of the serial bus include the following: a)Bus transactions that include both block and single quadlet reads and writes, as well as an モisochronousヤ mode that provides a low-overhead guaranteed bandwidth service. b)A ...


IEEE Standard for an 8-Bit Microcomputer Bus System: STD Bus


IEEE Standard for Boot (Initialization Configuration) Firmware: Bus Supplement for IEEE 1496 (SBus)


IEEE Standard for Module Test and Maintenance Bus (MTM-Bus) Protocol