Conferences related to DRAM chips

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2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


2020 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.


2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.



Periodicals related to DRAM chips

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Advanced Packaging, IEEE Transactions on

The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Components and Packaging Technologies, IEEE Transactions on

Component parts, hybrid microelectronics, materials, packaging techniques, and manufacturing technology.


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


Computer Architecture Letters

Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing



Most published Xplore authors for DRAM chips

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Xplore Articles related to DRAM chips

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A 16K × 1 bit dynamic RAM

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1977

None


A 5V-only 2K × 8 dynamic RAM

1979 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1979

A 5V-only 2K×8 dynamic RAM developed primarily for use in microprocessor systems will be discussed. The memory uses edge-activated design techniques to provide access time and power of 120ns and 150mW.


4-16Mb DRAMs: Cost/performance tradeoffs

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1986

This panel will try to assess the relative merits of alternative circuit design techniques and technology choices for 4-16Mb DRAMs. To illustrate: by including additional masking steps, improved performance may be obtained at increased cost. Other topics to be discussed will include the critical charge for smaller cells, alternative cell designs, package constraints, internal voltage levels, and the best choice ...


Stratified charge memory

1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1978

None


An NMOS DRAM controller

1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1982

An NMOS controller, generating control signals for a DRAM, with programmable interfaces, dual-port configurations and error correction support, will be discussed. The chip has a worst case delay of 35ns and can drive 500pF loads.



Educational Resources on DRAM chips

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IEEE-USA E-Books

  • A 16K × 1 bit dynamic RAM

    None

  • A 5V-only 2K × 8 dynamic RAM

    A 5V-only 2K×8 dynamic RAM developed primarily for use in microprocessor systems will be discussed. The memory uses edge-activated design techniques to provide access time and power of 120ns and 150mW.

  • 4-16Mb DRAMs: Cost/performance tradeoffs

    This panel will try to assess the relative merits of alternative circuit design techniques and technology choices for 4-16Mb DRAMs. To illustrate: by including additional masking steps, improved performance may be obtained at increased cost. Other topics to be discussed will include the critical charge for smaller cells, alternative cell designs, package constraints, internal voltage levels, and the best choice for interconnect. Finally, the expected time frames for experimental and production stages will be explored.

  • Stratified charge memory

    None

  • An NMOS DRAM controller

    An NMOS controller, generating control signals for a DRAM, with programmable interfaces, dual-port configurations and error correction support, will be discussed. The chip has a worst case delay of 35ns and can drive 500pF loads.

  • Yield model for 256K RAMs and beyond

    An updated yield model based on visual inspection, electrical tests, bit failure maps and failure analysis will be reported. The approach has been verified for the manufacture of 64K memories. It includes yield calculations for partially good product and redundancy and provides yield estimates for 128K and 256K chips.

  • A 64Kb MOS dynamic RAM

    A memory cell using a three-layer polysilicon process will be reported. Described, too, will be a dummy cell and sense amplifier configuration.

  • Where Are Cache Memories Going?

    In the span of only five years cache memories, once an arcane method of eking the last ounce of processing power from large mainframe computers, have become a household word. Caches are now offered in most high-end personal computers, as well as in all workstations. Caches offer a means of putting today's CPU architectures to their highest capability, without requiring massive changes in the direction of processing. This does not imply that we have reached a steady state, where the only developments to be expected will be improvements in CPU speed and cache size. The cache will be found to facilitate radical changes in computer architecture without requiring equivalent changes in CPU design. Caches are already being used to allow the implementation of tightly- coupled multiprocessor systems, some of whose throughputs are more than proportional to the number of processors used in the system.

  • A storage-node-boosted RAM with word line delay compensation

    A dynamic RAM architecture, storing 1.7V<inf>DD</inf>for '1' level in the cell without any boosted clocks and eliminating the word line delay by means of a pulsed cell plate, will be described.

  • A 4K × 8 dynamic RAM with self refresh

    A 5V-only 4K×8 dynamic RAM with multiplexed address/ data I/O and on-chip self-refresh will be described, The chip has been designed for use in 8b or 16b microprocessor systems.



Standards related to DRAM chips

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No standards are currently tagged "DRAM chips"