IEEE Organizations related to D-HEMTs

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Conferences related to D-HEMTs

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2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2017 IEEE 30th International Conference on Microelectronics (MIEL)

Meeting for Scientific/Academic researchers working in the field of microelectronics



Periodicals related to D-HEMTs

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Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.



Most published Xplore authors for D-HEMTs

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Xplore Articles related to D-HEMTs

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Implementation of GaAs E/D HEMT analog components for oversampling analog/digital conversion

Proceedings of 1994 IEEE GaAs IC Symposium, 1994

The paper presents design considerations and implementation of analog components, including an operational amplifier, latched comparator, 1 bit D/A converter and second-order modulator, for a fully differential delta-sigma modulation oversampling A/D converter in a 0.5 /spl mu/m GaAs E/D HEMT technology. On-wafer measurements demonstrate that the second-order modulator achieves a 60 dB dynamic range at a Nyquist conversion rate of ...


A high-speed resonant tunneling flip-flop circuit employing a monostable-bistable transition logic element (MOBILE) with an SCFL-type output buffer

Conference Proceedings. 1998 International Conference on Indium Phosphide and Related Materials (Cat. No.98CH36129), 1998

A resonant tunneling flip-flop circuit was fabricated based on a monostable- bistable transition logic element (MOBILE). In this work, an SCFL-type output buffer and depletion-mode HEMTs were employed in a different way to previous studies. A practical output voltage level close to the SCFL interface was first demonstrated with a MOBILE circuit operating at a high bit rate of up ...


A Gate Overdrive Protection Technique for Improved Reliability in AlGaN/GaN Enhancement-Mode HEMTs

IEEE Electron Device Letters, 2013

On a GaN smart power integrated-circuit platform, a monolithically integrated gate-protected high-voltage AlGaN/GaN enhancement-/depletion-mode high- electron mobility transistor (HEMT) has been proposed. It can sustain large input gate voltage swing (>; 20 V) with enhanced safety (no gate failure observed) and improved reliability (no observable shifting of the threshold voltage), and the breakdown voltage is not sacrificed. Such a protection ...


InP-based HEMTs for high speed, low power circuit applications

1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105), 1998

Processes for the monolithic integration of enhancement- and depletion-mode HEMTs (E/D-HEMTs) in the lattice matched InP material system are described. Using the buried Pt gate technology, 0.3 /spl mu/m gate-length E-HEMTs exhibiting a threshold voltage of +167 mV and a maximum extrinsic transconductance, g/sub mext/, of 700 mS/mm are demonstrated. D-HEMTs with corresponding device parameters of -443 mV and 462 ...


Performance analysis of monolithically integrated depletion-/enhancement-mode InAlN/GaN heterostructure HEMT transistors

2017 International Conference on Applied Electronics (AE), 2017

The paper addresses a top-down design flow of depletion-load digital inverter formed by monolithically integrated depletion-mode and enhancement-mode high electron mobility transistors (HEMTs) on common InAlN/GaN heterostructure grown on sapphire substrate. We describe the inverter design at transistor level using HSPICE models developed earlier. The inverter layout representation, which also defines the lithographic masks required for the fabrication process, is ...


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Educational Resources on D-HEMTs

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IEEE.tv Videos

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IEEE-USA E-Books

  • Implementation of GaAs E/D HEMT analog components for oversampling analog/digital conversion

    The paper presents design considerations and implementation of analog components, including an operational amplifier, latched comparator, 1 bit D/A converter and second-order modulator, for a fully differential delta-sigma modulation oversampling A/D converter in a 0.5 /spl mu/m GaAs E/D HEMT technology. On-wafer measurements demonstrate that the second-order modulator achieves a 60 dB dynamic range at a Nyquist conversion rate of 5.0 MHz with a sampling frequency of 500 MHz.

  • A high-speed resonant tunneling flip-flop circuit employing a monostable-bistable transition logic element (MOBILE) with an SCFL-type output buffer

    A resonant tunneling flip-flop circuit was fabricated based on a monostable- bistable transition logic element (MOBILE). In this work, an SCFL-type output buffer and depletion-mode HEMTs were employed in a different way to previous studies. A practical output voltage level close to the SCFL interface was first demonstrated with a MOBILE circuit operating at a high bit rate of up to 20 Gb/s. This indicates that the MOBILE has sufficient current drivability. Another advantage of employing an SCFL output buffer is also described. This is that D-HEMTs fabricated with precise gate-recess technology using an InP etch stopper can be used for MOBILEs. Good uniformity of the device parameters of the HEMTs and the RTDs were obtained simultaneously with this implementation. These results indicate the promise of using the MOBILE circuit in practical applications.

  • A Gate Overdrive Protection Technique for Improved Reliability in AlGaN/GaN Enhancement-Mode HEMTs

    On a GaN smart power integrated-circuit platform, a monolithically integrated gate-protected high-voltage AlGaN/GaN enhancement-/depletion-mode high- electron mobility transistor (HEMT) has been proposed. It can sustain large input gate voltage swing (>; 20 V) with enhanced safety (no gate failure observed) and improved reliability (no observable shifting of the threshold voltage), and the breakdown voltage is not sacrificed. Such a protection scheme with a wide input gate bias range also facilitates simple and reliable connections between the gate driver circuits and the power switches without the level shifter circuits for conventional GaN Schottky gate power HEMTs.

  • InP-based HEMTs for high speed, low power circuit applications

    Processes for the monolithic integration of enhancement- and depletion-mode HEMTs (E/D-HEMTs) in the lattice matched InP material system are described. Using the buried Pt gate technology, 0.3 /spl mu/m gate-length E-HEMTs exhibiting a threshold voltage of +167 mV and a maximum extrinsic transconductance, g/sub mext/, of 700 mS/mm are demonstrated. D-HEMTs with corresponding device parameters of -443 mV and 462 mS/mm are presented. Unity current gain cut-off frequencies of-over 95 GHz were obtained for these devices. Implementation of a divide-by-four prescaler in the direct coupled FET logic technology based on E- and D-HEMTs is demonstrated.

  • Performance analysis of monolithically integrated depletion-/enhancement-mode InAlN/GaN heterostructure HEMT transistors

    The paper addresses a top-down design flow of depletion-load digital inverter formed by monolithically integrated depletion-mode and enhancement-mode high electron mobility transistors (HEMTs) on common InAlN/GaN heterostructure grown on sapphire substrate. We describe the inverter design at transistor level using HSPICE models developed earlier. The inverter layout representation, which also defines the lithographic masks required for the fabrication process, is presented as well. The proposed mask set was designed taking into account the design-for-manufacturing approach. Furthermore, we evaluated measured properties and performance of the fabricated transistors and circuits and recalibrate the transistor models according to the latest measurements.

  • Low-Frequency-Noise Characteristic of Quasi-Enhancement-Mode HEMT Using a Selectively Hydrogen-Pretreatment

    The DC, RF, and low-frequency noise characteristics were investigated for a quasi-enhancement-mode (QE) HEMT using a selective hydrogen pretreatment (SHP). The QE-HEMT with SHP showed a large shift in threshold voltage without severe degradation of RF performances including cut-off frequency and maximum oscillation frequency, compared with those of HEMT without SHP. Moreover, the QE HEMT exhibited a reduction of low-frequency noise bulges compared with those of depletion-mode HEMT without an SHP, leading to an one-order smaller input noise spectral density at 100Hz, and offered a potential for application to a low phase noise oscillator

  • High-performance enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment

    We report a novel approach in fabricating high-performance enhancement mode (E-mode) AlGaN/GaN HEMTs. The fabrication technique is based on fluoride-based plasma treatment of the gate region in AlGaN/GaN HEMTs and post-gate rapid thermal annealing with an annealing temperature lower than 500/spl deg/C. Starting with a conventional depletion-mode HEMT sample, we found that fluoride-based plasma treatment can effectively shift the threshold voltage from -4.0 to 0.9 V. Most importantly, a zero transconductance (g/sub m/) was obtained at V/sub gs/=0 V, demonstrating for the first time true E-mode operation in an AlGaN/GaN HEMT. At V/sub gs/=0 V, the off-state drain leakage current is 28 μA/mm at a drain-source bias of 6 V. The fabricated E-mode AlGaN/GaN HEMTs with 1 μm-long gate exhibit a maximum drain current density of 310 mA/mm, a peak g/sub m/ of 148 mS/mm, a current gain cutoff frequency fTof 10.1 GHz and a maximum oscillation frequency fmaxof 34.3 GHz.

  • High-performance enhancement-mode InAlAs/InGaAs HEMTs using non-alloyed ohmic contact and Pt-based buried-gate

    In this paper, we demonstrate greatly improved R/sub S/ in an E-HEMT structure using non-alloyed ohmic contact and Pt-based buried gate approaches. First, the non-alloyed ohmic contact technique was used to produce very low contact resistance and to provide sharply defined ohmic edges. Second, in the fabrication of our E-HEMT's, we first intentionally fabricated depletion-mode HEMTs (D-HEMTs). Subsequently, by annealing the sample at 250/spl deg/C, these D-HEMTs were changed to E-HEMTs as a result of the Pt-InAlAs reaction taking place under the gate electrode, while the channel region between source and gate remained undepleted. This allowed a small R/sub S/ to be maintained An excellent transconductance (g/sub m/) of 1170 mS/mm was achieved for an E-HEMT with a 0.5-/spl mu/m-gate.

  • Monte Carlo simulation of HEMT

    Device simulation of HEMT (High Electron Mobility Transistor) has been carried out by ensemble Monte Carlo simulation. Since the electrons in HEMT are confined in GaAs region at the GaAs-AlGaAs hetero-interface, their motion is two-dimensional when the electron energy is low and thus we have to take into account the quantization of electrons at the interface. In order to develop a realistic device simulator of HEMT, we divide the channel region in meshes, and Schrodinger and Poisson equations are solved self-consistently to obtain electronic states of the two-dimensional electrons in a mesh. In addition the real space transfer from GaAs layer into AlGaAs barrier layer is taken into account.

  • 5 GHz /spl Sigma//spl Delta/ analog-to-digital converter with polarity alternating feedback comparator

    We designed and fabricated a 5 GHz oversampling, 100 MHz bandwidth continuous time second order /spl Sigma//spl Delta/ analog-to-digital converter (ADC) using 0.4-/spl mu/m InGaP/-InGaAs enhancement and depletion mode high electron mobility transistor (E/D HEMT) technology. We propose the polarity alternating feedback (PAF) technique for enhancing the sampling frequency and have applied it in the design of an ADC circuit. The fabricated ADC shows a signal-to-noise ratio (SNR) of 43 dB (7.3 bits) under a differential clock of 4.9 GHz with a power dissipation of 400 mW.



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