IEEE Organizations related to Cyclic redundancy check codes

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Conferences related to Cyclic redundancy check codes

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2020 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI)

This symposium pertains to the field of electromagnetic compatibility.


2020 IEEE International Magnetic Conference (INTERMAG)

INTERMAG is the premier conference on all aspects of applied magnetism and provides a range of oral and poster presentations, invited talks and symposia, a tutorial session, and exhibits reviewing the latest developments in magnetism.


GLOBECOM 2020 - 2020 IEEE Global Communications Conference

IEEE Global Communications Conference (GLOBECOM) is one of the IEEE Communications Society’s two flagship conferences dedicated to driving innovation in nearly every aspect of communications. Each year, more than 2,900 scientific researchers and their management submit proposals for program sessions to be held at the annual conference. After extensive peer review, the best of the proposals are selected for the conference program, which includes technical papers, tutorials, workshops and industry sessions designed specifically to advance technologies, systems and infrastructure that are continuing to reshape the world and provide all users with access to an unprecedented spectrum of high-speed, seamless and cost-effective global telecommunications services.


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


2020 IEEE International Conference on Image Processing (ICIP)

The International Conference on Image Processing (ICIP), sponsored by the IEEE SignalProcessing Society, is the premier forum for the presentation of technological advances andresearch results in the fields of theoretical, experimental, and applied image and videoprocessing. ICIP 2020, the 27th in the series that has been held annually since 1994, bringstogether leading engineers and scientists in image and video processing from around the world.



Periodicals related to Cyclic redundancy check codes

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Broadcasting, IEEE Transactions on

Broadcast technology, including devices, equipment, techniques, and systems related to broadcast technology, including the production, distribution, transmission, and propagation aspects.


Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Communications Letters, IEEE

Covers topics in the scope of IEEE Transactions on Communications but in the form of very brief publication (maximum of 6column lengths, including all diagrams and tables.)


Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...



Most published Xplore authors for Cyclic redundancy check codes

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Xplore Articles related to Cyclic redundancy check codes

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An integrated error correction and detection system for digital audio broadcasting

IEEE Transactions on Broadcasting, 2000

Hybrid in-band on-channel digital audio broadcasting systems deliver digital audio signals in such a way that is backward compatible with existing analog FM transmission. We present a channel error correction and detection system that is well-suited for use with audio source coders, such as the so-called perceptual audio coder (PAC), that have error concealment/mitigation capabilities. Such error mitigation is quite ...


Enhancement of turbo codes using cyclic redundancy check with interleaver optimisation

International Symposium onInformation Theory, 2004. ISIT 2004. Proceedings., 2004

A method is presented where a parallel concatenated convolutional code is preceded with a short cyclic redundancy check (CRC) without code rate loss. Parity bits are punctured and their place taken by the CRC. Results are given for the weight spectrum of an optimised code, rate 2/3, codeword length, n=1014 in comparison with an optimised, nonCRC code using the same ...


Error burst detection with high-rate convolutional codes

Proceedings of 1995 IEEE International Symposium on Information Theory, 1995

One crucial requirement for the use of convolutional codes in (only) error detection is low decoding complexity. We show that for this specific application the decoding complexity of convolutional codes is practically equal to the coding complexity, which is very small. Thus, the encoder/decoder can be implemented directly in hardware, or use efficient software decoding techniques like those used for ...


Arithmetic coding-based continuous error detection for efficient ARQ-based image transmission

IEEE Journal on Selected Areas in Communications, 2000

Block cyclic redundancy check (CRC) codes are typically used to perform error detection in automatic repeat request (ARQ) protocols for data communications. Although efficient, CRCs can detect errors only after an entire block of data has been received and processed. We propose a new "continuous" error detection scheme using arithmetic coding that provides a novel tradeoff between the amount of ...


An exact evaluation of the probability of undetected error for certain shortened binary CRC codes

MILCOM 88, 21st Century Military Communications - What's Possible?'. Conference record. Military Communications Conference, 1988

The authors give a computationally efficient algorithm for computing the probability of undetected error for a class of cyclic codes whose generator polynomial is equal to (x+1) times a primitive irreducible polynomial. This class contains three CRC (cyclic redundancy check) codes that have been adopted as international standards. The algorithm was used to compute the performance of a number of ...



Educational Resources on Cyclic redundancy check codes

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IEEE-USA E-Books

  • An integrated error correction and detection system for digital audio broadcasting

    Hybrid in-band on-channel digital audio broadcasting systems deliver digital audio signals in such a way that is backward compatible with existing analog FM transmission. We present a channel error correction and detection system that is well-suited for use with audio source coders, such as the so-called perceptual audio coder (PAC), that have error concealment/mitigation capabilities. Such error mitigation is quite beneficial for high quality audio signals. The proposed system involves an outer cyclic redundancy check (CRC) code that is concatenated with an inner convolutional code. The outer CRC code is used for error detection, providing flags to trigger the error mitigation routines of the audio decoder. The inner convolutional code consists of so- called complementary punctured-pair convolutional codes, which are specifically tailored to combat the unique adjacent channel interference characteristics of the FM band. We introduce a novel decoding method based on the so-called list Viterbi algorithm (LVA). This LVA-based decoding method, which may be viewed as a type of joint or integrated error correction and detection, exploits the concatenated structure of the channel code to provide enhanced decoding performance relative to decoding methods based on the conventional Viterbi algorithm (VA). We also present results of informal listening tests and other simulations on the Gaussian channel. These results include the preferred length of the outer CRC code for 96-kb/s audio coding and demonstrate that LVA-based decoding can significantly reduce the error flag rate relative to conventional VA-based decoding, resulting in dramatically improved decoded audio quality. Finally, we propose a number of methods for screening undetected errors in the audio domain.

  • Enhancement of turbo codes using cyclic redundancy check with interleaver optimisation

    A method is presented where a parallel concatenated convolutional code is preceded with a short cyclic redundancy check (CRC) without code rate loss. Parity bits are punctured and their place taken by the CRC. Results are given for the weight spectrum of an optimised code, rate 2/3, codeword length, n=1014 in comparison with an optimised, nonCRC code using the same rate and codeword length. Frame error rate performance achieved is within 0.36dB of the sphere packing bound constrained for binary transmission.

  • Error burst detection with high-rate convolutional codes

    One crucial requirement for the use of convolutional codes in (only) error detection is low decoding complexity. We show that for this specific application the decoding complexity of convolutional codes is practically equal to the coding complexity, which is very small. Thus, the encoder/decoder can be implemented directly in hardware, or use efficient software decoding techniques like those used for cyclic redundancy check (CRC) error detection codes. Different encoder/decoder implementations are considered. By studying the properties of high-rate convolutional codes for the purpose of error detection, we show their potential advantages over block codes. In addition, this study gives a deeper view of CRC codes-which happen to be a special case in a class of codes that we call unit-rate convolutional codes. Thus, for the extension of CRCs we can employ techniques used for convolutional codes, like the use of unit-memory or cyclic time-varying codes. Certain general error detection capabilities of the convolutional codes are derived.

  • Arithmetic coding-based continuous error detection for efficient ARQ-based image transmission

    Block cyclic redundancy check (CRC) codes are typically used to perform error detection in automatic repeat request (ARQ) protocols for data communications. Although efficient, CRCs can detect errors only after an entire block of data has been received and processed. We propose a new "continuous" error detection scheme using arithmetic coding that provides a novel tradeoff between the amount of added redundancy and the amount of time needed to detect an error once it occurs. This method of error detection, first introduced by Bell, Witten, and Cleary (1990), is achieved through the use of an arithmetic codec, and has the attractive feature that it can be combined physically with arithmetic source coding, which is widely used in state of-the-art image coders. We analytically optimize the tradeoff between added redundancy and error-detection time, achieving significant gains in bit rate throughput over conventional ARQ schemes for binary symmetric channel models for all probabilities of error.

  • An exact evaluation of the probability of undetected error for certain shortened binary CRC codes

    The authors give a computationally efficient algorithm for computing the probability of undetected error for a class of cyclic codes whose generator polynomial is equal to (x+1) times a primitive irreducible polynomial. This class contains three CRC (cyclic redundancy check) codes that have been adopted as international standards. The algorithm was used to compute the performance of a number of codes at various shortened block lengths, often with surprising results. It is suggested that, when dealing with shortened block lengths, one should choose a primitive polynomial with many rather than few nonzero coefficients in order to produce a good code.<<ETX>>

  • Soft-decision Decoding Of CRC Codes

    None

  • On computing undetected error probabilities on the Gilbert channel

    The authors examine methods for computing the probability of undetected error on the Gilbert channel. First, using Monte Carlo simulation they study the standard cyclic redundancy codes and compare the results with those on the binary symmetric channel. Then the authors consider a general method of approximate code evaluation which involves P(m,n), the probability of m errors in a block of length n bits. A nonrecursive technique for computing P(m,n) on the Gilbert channel is derived. Finally, it is shown how the symmetries of the Gilbert channel can lead to useful results for dealing with cyclic codes.<<ETX>>

  • Lowering error floors of irregular LDPC code on fast fading environment with and without perfect CSI

    Irregular LDPC codes can achieve better error rate performance than regular LDPC codes. However, irregular LDPC codes have higher error floors than regular LDPC codes. The ordered statistical decoding (OSD) algorithm achieves maximum likelihood (ML) decoding. ML decoding is effective in lowering error floors. However, temporal estimates obtained by the OSD algorithm satisfy the parity check equation of the LDPC code. The OSD algorithm cannot lower error floors because the temporal estimates satisfy the LDPC parity check equation. We proposed a concatenated code constructed with an inner irregular LDPC code and an outer cyclic redundancy check (CRC) code. Thanks to CRC, we can detect errors from the codeword estimated by the OSD algorithm. Our proposed LDPC code and decoding can lower error floors in an AWGN channel. However, in wireless access environments, we cannot neglect the effects of the channel. The OSD algorithm needs the ordering of each bit based on reliability. Channel state information (CSI) is used for deciding the reliability of each bit. We evaluate the block error rate (BLER) of the proposed LDPC code decoding in a fast fading channel with and without perfect CSI where 'without perfect CSI' means that only the average of the fading amplitudes is known at the receiver. By simulation, we show that the proposed LDPC code and decoding can lower error floors more than the conventional LDPC code with the OSD algorithm in fast fading channels with and without perfect CSI.

  • CRC-assisted error correction in a convolutionally coded system

    In communication systems employing a serially concatenated cyclic redundancy check (CRC) code along with a convolutional code (CC), erroneous packets after CC decoding are usually discarded. The list Viterbi algorithm (LVA) and the iterative Viterbi algorithm (IVA) are two existing approaches capable of recovering erroneously decoded packets. We here employ a soft decoding algorithm for CC decoding, and introduce several schemes to identify error patterns using the posterior information from the CC soft decoding module. The resultant iterative decoding-detecting (IDD) algorithm improves error performance by iteratively updating the extrinsic information based on the CRC parity check matrix. Assuming errors only happen in unreliable bits characterized by small absolute values of the log-likelihood ratio (LLR), we also develop a partial IDD (P-IDD) alternative which exhibits comparable performance to IDD by updating only a subset of unreliable bits. We further derive a soft-decision syndrome decoding (SDSD) algorithm, which identifies error patterns from a set of binary linear equations derived from CRC syndrome equations. Being noniterative, SDSD is able to estimate error patterns directly from the decoder output. The packet error rate (PER) performance of SDSD is analyzed following the union bound approach on pairwise errors. Simulations indicate that both IDD and IVA are better tailored for single parity check (PC) codes than for CRC codes. SDSD outperforms both IDD and LVA with weak CC and strong CRC. Applicable to AWGN and flat fading channels, our algorithms can also be extended to turbo coded systems.

  • On computing undetected error probabilities on the Gilbert channel

    Two methods for computing the probability of undetected error on the Gilbert (1960) channel are examined. First, using a method proposed by Kittel (1978), we study some standard cyclic redundancy codes and compare the results with those on the binary symmetric channel. Then we consider a general method of approximate code evaluation, proposed by Elliott, which involves P(m, n), the probability of m errors in a block of length n bits. A nonrecursive technique for computing P(m, n) on the Gilbert channel is described.



Standards related to Cyclic redundancy check codes

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IEEE Recommended Practice for Data Communications Between Remote Terminal Units and Intelligent Electronic Devices in a Substation

This project will make the Trial Use document a full Recommended Practice. The present standard was published in March 1998 as a Trial Use Recommended Practice. However, the protocols listed in the document were actually selected by the Task Force in 1995. It has already shown to be a valuable standard and is being widely used in the industry.