Conferences related to Design Productivity

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2021 IEEE Photovoltaic Specialists Conference (PVSC)

Photovoltaic materials, devices, systems and related science and technology


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE 17th Annual Consumer Communications & Networking Conference (CCNC)

IEEE CCNC 2020 will present the latest developments and technical solutions in the areas of home networking, consumer networking, enabling technologies (such as middleware) and novel applications and services. The conference will include a peer-reviewed program of technical sessions, special sessions, business application sessions, tutorials, and demonstration sessions.


2020 IEEE Frontiers in Education Conference (FIE)

The Frontiers in Education (FIE) Conference is a major international conference focusing on educational innovations and research in engineering and computing education. FIE 2019 continues a long tradition of disseminating results in engineering and computing education. It is an ideal forum for sharing ideas, learning about developments and interacting with colleagues inthese fields.


2020 IEEE International Conference on Industrial Engineering and Engineering Management (IEEM)

All topics related to engineering and technology management, including applicable analytical methods and economical/social/human issues to be considered in making engineering decisions.


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Periodicals related to Design Productivity

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Automation Science and Engineering, IEEE Transactions on

The IEEE Transactions on Automation Sciences and Engineering (T-ASE) publishes fundamental papers on Automation, emphasizing scientific results that advance efficiency, quality, productivity, and reliability. T-ASE encourages interdisciplinary approaches from computer science, control systems, electrical engineering, mathematics, mechanical engineering, operations research, and other fields. We welcome results relevant to industries such as agriculture, biotechnology, healthcare, home automation, maintenance, manufacturing, pharmaceuticals, retail, ...


Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


Computer Graphics and Applications, IEEE

IEEE Computer Graphics and Applications (CG&A) bridges the theory and practice of computer graphics. From specific algorithms to full system implementations, CG&A offers a strong combination of peer-reviewed feature articles and refereed departments, including news and product announcements. Special Applications sidebars relate research stories to commercial development. Cover stories focus on creative applications of the technology by an artist or ...


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


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Most published Xplore authors for Design Productivity

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Xplore Articles related to Design Productivity

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Graduate Education to Fight System Level Design Productivity Gap in SOC Design

2007 IEEE International Conference on Microelectronic Systems Education (MSE'07), 2007

Design productivity gap in system on chip (SOC) design is the most severe challenge for continuous growth of the semiconductor industry. Considerable pressure is put on EDA research to come up with appropriate electronic system level (ESL) design methodologies in order to meet stringent time to market (TTM) constraints in this very cost sensitive industry. Multiple abstraction levels and platform ...


A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Compared to the use of a typical software development flow, the productivity of developing FPGA-based compute applications remains much lower. Although the use of high-level synthesis (HLS) tools may partly alleviate this shortcoming, the lengthy low-level FPGA implementation process remains a major obstacle to high productivity computing, limiting the number of compile-debug-edit cycles per day. Furthermore, high-level application developers often ...


FPGA design productivity a discussion of the state of the art and a research agenda

2008 International Conference on Field-Programmable Technology, 2008

Summary form only given. As configurable computing matures there is continued interest in design productivity. While configurable computing machines (CCMs) are touted as re-usable, re-configurable platforms for accelerated computing, the design processes and tools employed to map applications to such platforms may have more in common with hardware ASIC design tools and processes than with conventional software development tools and ...


Design productivity of a high level synthesis compiler versus HDL

2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2016

The complexity of hardware systems is currently growing faster than the productivity of system designers and programmers. This phenomenon is called Design Productivity Gap and results in inflating design costs. In this paper, the notion of Design Productivity is precisely defined, as well as a metric to assess the Design Productivity of a High-Level Synthesis (HLS) method versus a manual ...


Quantifying design productivity: an effort distribution analysis

Proceedings of EURO-DAC. European Design Automation Conference, 1995

This paper presents basic process models for textual and graphical HDL-based design. The models are used to measure effort (time) required for various design activities, with an aim to quantify design productivity. Effort- distribution in man-minutes is used as a parameter to evaluate design productivity. Design quality, defined as a probability that the design meets its specifications, is plotted for ...


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Educational Resources on Design Productivity

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IEEE-USA E-Books

  • Graduate Education to Fight System Level Design Productivity Gap in SOC Design

    Design productivity gap in system on chip (SOC) design is the most severe challenge for continuous growth of the semiconductor industry. Considerable pressure is put on EDA research to come up with appropriate electronic system level (ESL) design methodologies in order to meet stringent time to market (TTM) constraints in this very cost sensitive industry. Multiple abstraction levels and platform based design methodologies have been the primary answers to this challenge. In this paper we describe our experience of a project oriented SOC graduate level course which combines the learning of multiple abstraction levels and platform based design to fight fixed amount of course time and time constrained learning curves to educate future engineers.

  • A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency

    Compared to the use of a typical software development flow, the productivity of developing FPGA-based compute applications remains much lower. Although the use of high-level synthesis (HLS) tools may partly alleviate this shortcoming, the lengthy low-level FPGA implementation process remains a major obstacle to high productivity computing, limiting the number of compile-debug-edit cycles per day. Furthermore, high-level application developers often lack the intimate hardware engineering experience that is needed to achieve high performance on FPGAs, therefore undermining their usefulness as accelerators. To address the productivity and performance problems, a HLS methodology that utilizes soft coarse-grained reconfigurable arrays (SCGRAs) as an intermediate compilation step is presented. Instead of compiling high-level applications directly to circuits, the compilation process is reduced to an operation scheduling task targeting the SCGRA.

  • FPGA design productivity a discussion of the state of the art and a research agenda

    Summary form only given. As configurable computing matures there is continued interest in design productivity. While configurable computing machines (CCMs) are touted as re-usable, re-configurable platforms for accelerated computing, the design processes and tools employed to map applications to such platforms may have more in common with hardware ASIC design tools and processes than with conventional software development tools and processes. To address this there continues to be research in the community on higher-level languages, reusable core libraries, improved CAD tools, debug infrastructure, etc. but little focus on the big picture. That is, how do all these pieces fit together into a comprehensive approach for improving design productivity? Is a 10x increase in design productivity feasible in the next few years? How about 20x? What are the key research problems that must be solved? What are the most promising approaches to solving these problems? My talk will focus on these questions and will draw from the results of two events related to FPGA design productivity which were held recently. First, the day before FPT'2009, a workshop is being held at Taiwan National University to discuss these questions with all FPT attendees invited to participate. Details are found on the FPT conference website. Special guest speakers at the workshop will be asked to provide their viewpoints on FPGA design productivity and components of a research agenda to increase productivity over the next 5-10 year horizon. Second, during the past year in the United States, two multi-university research teams have focused on developing and outlining a research agenda to address FPGA design productivity, culminating in a workshop held in Salt Lake City during June 2008. My talk will discuss the current challenges in FPGA design productivity and address a range of solutions, based in part on the results of the above two workshops as well as other efforts going on in the research community.

  • Design productivity of a high level synthesis compiler versus HDL

    The complexity of hardware systems is currently growing faster than the productivity of system designers and programmers. This phenomenon is called Design Productivity Gap and results in inflating design costs. In this paper, the notion of Design Productivity is precisely defined, as well as a metric to assess the Design Productivity of a High-Level Synthesis (HLS) method versus a manual hardware description. The proposed Design Productivity metric evaluates the trade-off between design efficiency and implementation quality. The method is generic enough to be used for comparing several HLS methods of different natures, opening opportunities for further progress in Design Productivity. To demonstrate the Design Productivity evaluation method, an HLS compiler based on the CAPH language is compared to manual VHDL writing. The causes that make VHDL lower level than CAPH are discussed. Versions of the sub-pixel interpolation filter from the MPEG HEVC standard are implemented and a design productivity gain of 2.3× in average is measured for the CAPH HLS method. It results from an average gain in design time of 4.4× and an average loss in quality of 1.9×.

  • Quantifying design productivity: an effort distribution analysis

    This paper presents basic process models for textual and graphical HDL-based design. The models are used to measure effort (time) required for various design activities, with an aim to quantify design productivity. Effort- distribution in man-minutes is used as a parameter to evaluate design productivity. Design quality, defined as a probability that the design meets its specifications, is plotted for various design activities. We also discuss the resources that are essential to perform each design activity. These experiments demonstrate that "effort-distribution analysis" is useful for real life HDL-based design projects.

  • Measuring HDL-based design productivity: an experimental comparison

    Two process models for top-down HDL-based design are developed in order to measure HDL-based design productivity. A sorting algorithm is used as a benchmark to experience various design activities in HDL entry and mixed entry design process models. We measure the effort (time) required for each design activity and analyze the "effort-distribution" over various design activities. We also discuss the resources that are essential to perform each design activity. These experiments the applicability of "effort-distribution analysis" to enhance design productivity in real life design projects.

  • The impact of technology on product design, productivity, and profits: a duopoly model of price-quality competition

    This paper develops a two stage economic model of duopoly competition to examine the impact of technology investments in product design tools on product quality and price, firm productivity and profits, and consumer welfare. In the first stage the firms simultaneously choose product quality and in the second stage, after observing each other's quality choices, the firms simultaneously set prices. This model captures the firm's option to leverage technology tools to improve product quality and tracks the effect of such quality adjustments on measures of firm performance and consumer welfare. More specifically, the findings show that profit-maximizing firms leverage technology-based design tools to improve product quality, resulting in higher levels of firm profits and consumer welfare; however, these improvements come at the expense of productivity. Alternatively, the findings show that firms that fail to improve quality, and instead leverage the tools to reduce production costs, realize higher levels of productivity; however, this improvement in productivity comes at the expense of profits and consumer welfare. The results of the analytical model cast a new light on why it may be reasonable to empirically observe reductions in firm productivity following investments in IT tools that improve production capabilities.

  • How to increase ICs design productivity: one of the approaches

    Reasons of microelectronics design productivity decreasing have been analysed. Decreasing of students' interest in studies of electronics and microelectronics design is determined as one of the main reason of the shortage of ICs designers. The necessity of the development the new approaches for raising interest in microelectronics studies addressed to high school students is substantiated.

  • System-level modeling and validation increase design productivity and save errors

    As the complexity of system on chip (SoC) devices rises to include scores, in some cases hundreds, of distinct blocks, system validation becomes a critical concern. A variety of techniques have emerged to help designers verify that individual blocks of a device meet performance specification. But what about functional intent? Are performance goals achieved? In this paper, we make the case for high-level system validation before RTL implementation, and present a flow to approach this increasingly essential task.

  • Studies in VLSI technology economics. IV. Models for gate array design productivity

    An empirical model of design productivity is presented and its implications for current and future design are discussed. Model and observed values correlate well (the correlation coefficient is 0.85). The analysis encompasses 70 designs, primarily gate arrays, of up to 25000 gates from five major corporations, designed during 1983-8. The estimate of design productivity enables the determination of normalized productivity, manpower, and schedule. The normalized design productivity adjusts for differences in the design tasks, permitting standardized productivity measurements for planning and for benchmarking.<<ETX>>



Standards related to Design Productivity

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Recommended Practice for the Internet - Web Site Engineering, Web Site Management and Web Site Life Cycle

Define recommended practices for World Wide Web page engineering for Intranet and Extranet environments, based on World Wide Web Consortium (W3C) and related industry guidelines. (Expanded from previous PAR which specifically mentioned HTML and XML)