Conferences related to Coprocessors

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2023 Annual International Conference of the IEEE Engineering in Medicine & Biology Conference (EMBC)

The conference program will consist of plenary lectures, symposia, workshops and invitedsessions of the latest significant findings and developments in all the major fields of biomedical engineering.Submitted full papers will be peer reviewed. Accepted high quality papers will be presented in oral and poster sessions,will appear in the Conference Proceedings and will be indexed in PubMed/MEDLINE.


2020 IEEE International Symposium on Antennas and Propagation and North American Radio Science Meeting

The joint meeting is intended to provide an international forum for the exchange of information on state of the art research in the area of antennas and propagation, electromagnetic engineering and radio science


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 59th IEEE Conference on Decision and Control (CDC)

The CDC is the premier conference dedicated to the advancement of the theory and practice of systems and control. The CDC annually brings together an international community of researchers and practitioners in the field of automatic control to discuss new research results, perspectives on future developments, and innovative applications relevant to decision making, automatic control, and related areas.


2020 IEEE International Conference on Consumer Electronics (ICCE)

The International Conference on Consumer Electronics (ICCE) is soliciting technical papersfor oral and poster presentation at ICCE 2018. ICCE has a strong conference history coupledwith a tradition of attracting leading authors and delegates from around the world.Papers reporting new developments in all areas of consumer electronics are invited. Topics around the major theme will be the content ofspecial sessions and tutorials.


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Periodicals related to Coprocessors

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Communications Magazine, IEEE

IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...


Computer Architecture Letters

Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing


Computer Graphics and Applications, IEEE

IEEE Computer Graphics and Applications (CG&A) bridges the theory and practice of computer graphics. From specific algorithms to full system implementations, CG&A offers a strong combination of peer-reviewed feature articles and refereed departments, including news and product announcements. Special Applications sidebars relate research stories to commercial development. Cover stories focus on creative applications of the technology by an artist or ...


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Computing in Science & Engineering

Physics, medicine, astronomy—these and other hard sciences share a common need for efficient algorithms, system software, and computer architecture to address large computational problems. And yet, useful advances in computational techniques that could benefit many researchers are rarely shared. To meet that need, Computing in Science & Engineering (CiSE) presents scientific and computational contributions in a clear and accessible format. ...


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Most published Xplore authors for Coprocessors

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Xplore Articles related to Coprocessors

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Reduced instruction set computers

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1986

The infulential computer architects believe that conventional microprocessor architectures have reached a performance limit and represent a dead end in processor evolution. A new approach, the Reduced Instruction Set Computer (RISC) has emerged from research laboratories and is poised to enter the marketplace. RISC processors achieve performance by a careful selection and streamlining of the instruction set making possible a ...


A numeric data processor

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1980

A 4-state HMOS ROM, with nearly 700 bits of RAM for an internal stack and 29,000 bits of ROM for microcode and constants for a math processor, will be described. To integrate multiply, divide, square root and transcendental functions, a 68-bit internal data path has been included, with fast shifter and allied hardware to correct rounding.


Implementation options for WCDMA

2000 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.00CH37100), 2000

This paper discusses the design tradeoffs and implementation options for building wideband CDMA systems. System on a chip (SOC) solutions have a range of implementation options, from processor cores to custom ASIC (or a mix of both), to satisfy the extremely challenging requirements of the digital baseband of a next generation wireless system. Additionally, good designs should have a roadmap ...


A High-Speed Vision System for Moment-Based Analysis of Numerous Objects

2007 IEEE International Conference on Image Processing, 2007

We describe a high-speed vision system for real-time applications, which is capable of processing visual information at a frame rate of 1 kfps, including both imaging and processing. Our system performs moment-based analysis of numerous objects. Moments are useful values providing information about geometric features and invariant features with respect to image-plane transformations. In addition, the simultaneous observation of numerous ...


Design a co-processor for Output Probability Calculation in speech recognition

2009 IEEE International Symposium on Circuits and Systems, 2009

In the CHMM (Continuous Hidden Markov Model) based speech recognition algorithm, Output Probability Calculation (OPC) is the most computation- intensive part. To reduce power consumption and design cost, this paper presents a custom-designed co-processor to implement OPC. The standard SRAM interface of the co-processor allows it to be controlled by various micro- controllers. The co-processor has been implemented in standard-cell ...


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Educational Resources on Coprocessors

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IEEE.tv Videos

No IEEE.tv Videos are currently tagged "Coprocessors"

IEEE-USA E-Books

  • Reduced instruction set computers

    The infulential computer architects believe that conventional microprocessor architectures have reached a performance limit and represent a dead end in processor evolution. A new approach, the Reduced Instruction Set Computer (RISC) has emerged from research laboratories and is poised to enter the marketplace. RISC processors achieve performance by a careful selection and streamlining of the instruction set making possible a high-performance pipelined implementation. But not all microprocessor designers agree with the RISC approach. Panelists will address the future role of RISC and whether it will displace conventional architectures in the next generation. To be debated is whether or not there is a need for a new architecture, even if technically superior, in the existing volume marketplace. Possibly, as technology advancements appear, the mood could change during the next five years.

  • A numeric data processor

    A 4-state HMOS ROM, with nearly 700 bits of RAM for an internal stack and 29,000 bits of ROM for microcode and constants for a math processor, will be described. To integrate multiply, divide, square root and transcendental functions, a 68-bit internal data path has been included, with fast shifter and allied hardware to correct rounding.

  • Implementation options for WCDMA

    This paper discusses the design tradeoffs and implementation options for building wideband CDMA systems. System on a chip (SOC) solutions have a range of implementation options, from processor cores to custom ASIC (or a mix of both), to satisfy the extremely challenging requirements of the digital baseband of a next generation wireless system. Additionally, good designs should have a roadmap that will take advantage of rapid improvements in process technology. This paper describes the use of coprocessors alongside DSPs to meet the demanding computational requirements of WCDMA. We show that a coprocessor based design still achieves reasonably efficient area and power use, maintains a high degree of programmability and has a good technology migration path.

  • A High-Speed Vision System for Moment-Based Analysis of Numerous Objects

    We describe a high-speed vision system for real-time applications, which is capable of processing visual information at a frame rate of 1 kfps, including both imaging and processing. Our system performs moment-based analysis of numerous objects. Moments are useful values providing information about geometric features and invariant features with respect to image-plane transformations. In addition, the simultaneous observation of numerous objects allows recognition of various complex phenomena. The proposed system achieves high-speed image processing by providing a dedicated massively parallel co- processor for moment extraction. The co-processor has a high-performance core based on a pixel-parallel and object-parallel calculation method. We constructed a prototype system and evaluated its performance. We present results obtained in actual operation.

  • Design a co-processor for Output Probability Calculation in speech recognition

    In the CHMM (Continuous Hidden Markov Model) based speech recognition algorithm, Output Probability Calculation (OPC) is the most computation- intensive part. To reduce power consumption and design cost, this paper presents a custom-designed co-processor to implement OPC. The standard SRAM interface of the co-processor allows it to be controlled by various micro- controllers. The co-processor has been implemented in standard-cell based approach and manufactured in 0.18 mum UMC technology. Tested with a 358-state 3-mixture 27-feature 800-word HMM, the co-processor operates at 10 MHz to meet real-time requirement. The power consumption of this co-processor is 1.6 mW, and the die size is 1.18 mm<sup>2</sup>.

  • A reconfigurable channel codec coprocessor for software radio multimedia applications

    This paper describes a coprocessor architecture for channel coding and decoding in software radio high bit rate applications. The proposed approach has been implemented in VHDL code. After a brief introduction about main target applications, and the motivation for the proposed architecture, we show the high level device layout, dwelling upon every single entity. Coprocessor functional behaviour has been analyzed by a Visual C++ simulator designed to this aim; in this document we show some of the most significant simulation results.

  • High Throughput Systolic SOM IP Core for Fpgas

    We have designed a modular SOM systolic architecture that can classify data vectors with thousands of elements in real time. The architecture is described as a soft IP core in synthesizable VHDL. The SOM neural network size, the input data vectors dimension, the weight and data element bitwidth precision etc. are all designer tunable parameters. Several SOM neural network instances have been synthesized and their performance evaluated for different Xilinx Virtex-II and Virtex II-Pro FPGAs. Moderate to large size SOM networks that can process data vectors with as many as 4096 elements can fit into a single FPGA device and clocked at frequencies as high as 150 MHz. This makes the architecture a useful co-processor candidate for the real-time categorization of large-size genomics and proteomics datasets.

  • Reliability Prediction of the Series System with Spares Subject to Weibull Failures

    None

  • A 32 b 64-matrix parallel CMOS processor

    The /spl beta/ chip is a 32 b floating-point processor with 64-matrix parallel computing units using CMOS 0.35 /spl mu/m technology. The /spl beta/ chip is intended for use as a DSP coprocessor in a PC environment or in other computational-intensive applications. Such applications include digital filter (FIR, IIR), matrix multiplication, nonlinear polynomial calculations, DCT, DFT, video compression, and 3D graphics. In each computing unit (CU), all calculations are in the logarithm domain except some special instructions. The absolute error using the logarithm operation is less than 1 LSB in IEEE 32 b floating-point format. There is a 128/spl times/32 b memory (cache) in each CU. The total memory (cache) is 32 kB on the chip. There are three I/O buses on the chip; input data bus, output data bus and host control bus. The average sustained performance can reach 10 GFLOPS.

  • The design of digital fault recorder module based on S12XD

    The hardware architecture and software designs of the digital fault recorder module are described in this paper. The enhanced MSCAN module and the XGATE co-processor of S12XD MCU are used to receive and manage the operate data through high-speed CAN bus. F-RAM is used as non-volatile data storage memory. The software, especially mentioned XGATE and fault data storage strategy, is discussed in detail. This module has been applied in the distributed generator excitation equipment.



Standards related to Coprocessors

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No standards are currently tagged "Coprocessors"