35,809 resources related to Design methodology
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the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.
The Frontiers in Education (FIE) Conference is a major international conference focusing on educational innovations and research in engineering and computing education. FIE 2019 continues a long tradition of disseminating results in engineering and computing education. It is an ideal forum for sharing ideas, learning about developments and interacting with colleagues inthese fields.
APEC focuses on the practical and applied aspects of the power electronics business. Not just a power designer’s conference, APEC has something of interest for anyone involved in power electronics including:- Equipment OEMs that use power supplies and converters in their equipment- Designers of power supplies, dc-dc converters, motor drives, uninterruptable power supplies, inverters and any other power electronic circuits, equipments and systems- Manufacturers and suppliers of components and assemblies used in power electronics- Manufacturing, quality and test engineers involved with power electronics equipment- Marketing, sales and anyone involved in the business of power electronic- Compliance engineers testing and qualifying power electronics equipment or equipment that uses power electronics
The conference program will consist of plenary lectures, symposia, workshops and invitedsessions of the latest significant findings and developments in all the major fields of biomedical engineering.Submitted papers will be peer reviewed. Accepted high quality papers will be presented in oral and postersessions, will appear in the Conference Proceedings and will be indexed in PubMed/MEDLINE
The International Conference on Robotics and Automation (ICRA) is the IEEE Robotics and Automation Society’s biggest conference and one of the leading international forums for robotics researchers to present their work.
The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.
The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.
Experimental and theoretical advances in antennas including design and development, and in the propagation of electromagnetic waves including scattering, diffraction and interaction with continuous media; and applications pertinent to antennas and propagation, such as remote sensing, applied optics, and millimeter and submillimeter wave techniques.
The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...
The IEEE Reviews in Biomedical Engineering will review the state-of-the-art and trends in the emerging field of biomedical engineering. This includes scholarly works, ranging from historic and modern development in biomedical engineering to the life sciences and medicine enabled by technologies covered by the various IEEE societies.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Three-dimensional integrated circuit (3D-IC) is considered to be the most promising technology for modern and future electronic devices manufacturing. However, lots of challenges need to be addressed in order to make 3D-IC technically feasible as well as cost effective. One of the major challenges for 3D-IC is electronic design automation (EDA) due to the lack of true 3D EDA tools. ...
2011 IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC), 2011
Nowadays, with the processing technology of integrated circuits(IC) developing into deep sub-micron size and the scale of IC running into VLSI, the existing IC design methodology can hardly meet the demands for short time-to-market and continuous increasing functionality of IC products. Facing with these challenges, researchers all around the world have been chasing rapid design methods such as reconfigurable processor ...
Proceedings Frontiers in Education 35th Annual Conference, 2005
A rapid register-transfer level (RTL) embedded processor platform design methodology that is included as an educational tool for a special topic is introduced. In the special topic, rapid digital system design from digital fundamentals to processor platforms is practiced using a top-down design methodology with both Verilog hardware description language (HDL) and VHDL. In addition, all of the RTL design ...
2018 IEEE 7th Global Conference on Consumer Electronics (GCCE), 2018
In this paper, a mixed-level design methodology for digitally controlled power converter IC is proposed. The proposed design methodology can reduce time for debugging and accelerate design period for digitally controlled power converter IC designers. With proper mixing of behavioral model, register- transfer level (RTL) model and transistor level model, the simulation can be more time effective without losing accuracy. ...
2015 IEEE Applied Power Electronics Conference and Exposition (APEC), 2015
In this work a standard design methodology with high accuracy and suitable for different PT (Piezoelectric-Transformer) based load resonant converters has been developed. With this methodology, a complete converter parameter design, optimization or even PT parameter evaluation can be done in a short time. The necessary inputs of the design flow are the specifications of the converter, such as minimum ...
Micro-Apps 2013: Design Methodology for GaAs MMIC PA
ICASSP 2011 Trends in Design and Implementation of Signal Processing Systems
Heuristics for Design for Reliability in Electrical and Electronic Products
Micro-Apps 2013: How to Make Your Designs More Robust
SOC DESIGN METHODOLOGY FOR IMPROVED ROBUSTNESS
Honors 2020: Susumu Kohyama Wins the IEEE Robert N. Noyce Medal
How to Optimize the Performance of Your RF Layout: MicroApps 2015 - Keysight Technologies
CIRCUIT DESIGN USING FINFETS
High Frequency Magnetic Circuit Design for Power Electronics
A 28nm, 475mW, 0.4-to-1.7GHz Embedded Transceiver Front-End Enabling High-Speed Data Streaming Within Home Cable Networks: RFIC Industry Showcase
Millimeter Wave Mobile Communications for 5G Cellular: It Will Work!
Tutorial: Model Predictive Control of Power Electronic Converters, Part Two, Tomislav Dragicevic - IECON 2018
Tutorial: Model Predictive Control of Power Electronic Converters, Part One, Jose Rodriguez - IECON 2018
Mapping Human to Robot Motion with Functional Anthropomorphism for Teleoperation and Telemanipulation with Robot Arm Hand Systems
Standards Education: Creating Global Standards (Chinese subtitles)
IMS 2011 Microapps - Online Design
KeyTalk with Conor Quinn: Empowering the Electronics Industry - A Power Technology Roadmap - APEC 2017
Standards Education: Creating Global Standards (English)
IEEE Authoring Part 4: Paper Structure
Three-dimensional integrated circuit (3D-IC) is considered to be the most promising technology for modern and future electronic devices manufacturing. However, lots of challenges need to be addressed in order to make 3D-IC technically feasible as well as cost effective. One of the major challenges for 3D-IC is electronic design automation (EDA) due to the lack of true 3D EDA tools. In this paper, we propose a novel design methodology which makes current (2D-IC) EDA tools 3D aware. This methodology can be applied to 3D-ICs with the structure of 2 tiers bonded face to face. Since the process node for each tier of the applied 3D-IC can be different, we name it Hybrid Process 3D- IC. Based on the hierarchical design methodology, low power design techniques, flip-chip physical implementation methods, customized cell libraries and scripts are combined together to build up Hybrid Process 3D-IC design methodology. In order to verify the proposed methodology, a real circuit is designed according to it. The detail of the circuit will be described in the following paragraphs.
Nowadays, with the processing technology of integrated circuits(IC) developing into deep sub-micron size and the scale of IC running into VLSI, the existing IC design methodology can hardly meet the demands for short time-to-market and continuous increasing functionality of IC products. Facing with these challenges, researchers all around the world have been chasing rapid design methods such as reconfigurable processor and high-level synthesis (HLS). In this paper, a transitional language for scheduling analysis in operator design methodology, which is a novel scheme of HLS, is proposed. With the help of the proposed transition language, an algorithm developed with high-level language can be transformed into hardware description automatically or half- automatically. The experiment results by applying a widely used target algorithm in the academic HLS field prove the feasibility and efficiency of the operator design methodology and also the proposed transition language comparing with that of the SPARK HLS tool developed by UC San Diego.
A rapid register-transfer level (RTL) embedded processor platform design methodology that is included as an educational tool for a special topic is introduced. In the special topic, rapid digital system design from digital fundamentals to processor platforms is practiced using a top-down design methodology with both Verilog hardware description language (HDL) and VHDL. In addition, all of the RTL design and verification processes can be rapidly and systematically performed through the methodology. Furthermore, a hierarchical RTL post-simulation verification methodology and a supporting tool can provide a rapid, flexible, and affordable verification environment for the field- programmable gate array (FPGA)-based embedded processor platform developed in the classroom. This methodology leads to the rapid development of embedded processor platforms for use in academia
In this paper, a mixed-level design methodology for digitally controlled power converter IC is proposed. The proposed design methodology can reduce time for debugging and accelerate design period for digitally controlled power converter IC designers. With proper mixing of behavioral model, register- transfer level (RTL) model and transistor level model, the simulation can be more time effective without losing accuracy. The proposed design methodology is demonstrated with digital control voltage mode buck converter IC and the chip was manufactured by TSMC 0.18-μm CMOS process. The measurement results shows the consistent with simulation results. In addition, simulation time is much less than traditional design methodology.
In this work a standard design methodology with high accuracy and suitable for different PT (Piezoelectric-Transformer) based load resonant converters has been developed. With this methodology, a complete converter parameter design, optimization or even PT parameter evaluation can be done in a short time. The necessary inputs of the design flow are the specifications of the converter, such as minimum input voltage, switching frequency, output voltage and output power, based on which the PT will be designed first. The output of the design flow is an appropriately designed input inductor, which meets the requirement of the specification. This design method can help designer to avoid repetitive simulations and generate optimized design parameters.
Field-programmable gate arrays (FPGAs) are used in various systems that use reconfigurable function. Conventional FPGAs have been developed by a transistor-level description for minimizing routing delay. Although FPGAs developed by the register transfer level (RTL) design methodology provide various benefits to the designers of a system-on-a-chip (SoC), they have not been realized. Therefore, the authors have advanced their development. They should be shown to operate in a practical throughput. For this purpose, circuits on them need to be designed and evaluated. In this paper, a ripple- carry adder (RCA) is designed on them and the throughput of the RCA is evaluated. The throughput shows that it is applicable to network processors. In addition, a wave-pipelined operation without changing the RCA reveals that the problem of routing delay in the FPGAs developed by the RTL methodology is mitigated.
The NoC (network-on-chip) paradigm is commonly considered as an aggressive long-term approach for on-chip communication. Interconnection networks of regular topologies can be designed as IP cores to reduce the well known design-productivity gap. Therefore, regular topologies are more preferred than irregular topologies. To solve the scalability problem of the NoC designs with homogeneous regular topologies, we propose a new NoC design methodology that uses heterogeneous regular topologies. We illustrate the proposed heterogeneous design methodology with a simple configurable regular interconnect topology set, which consists of three subtopologies with different network performances and silicon overheads. Evaluation of the three subtopologies reveals that subtopologies with more connections result in better network performance and more wire complexity. The contribution of the proposed heterogeneous design methodology is that it provides a flexible way to scale the interconnection networks of regular topologies according to the traffic requirements.
Processing of nonstationary one-dimensional and two-dimensional (2D) signals are usually performed by using high numerically consuming time-frequency and space/spatial-frequency (S/SF) tools, respectively. Being numerically quite complex, these solutions require significant time for calculation and then are usually unsuitable for real-time analysis, but also their application is severely restricted in practice. Hardware implementations, when possible, can overcome these problems. Besides, numerical complexity greatly increases in the 2D signals case, so that demands for hardware implementations of systems for processing of these signals, including their filtering, are more emphasized. However, chip dimensions are significantly enlarged in this case, as well as the power consumption and cost, while the processing speed is seriously reduced. Therefore, having in mind technology limitations in hardware realizations, these systems usually cannot be implemented. To overcome these problems, the register transfer level (RTL) design methodology- based and signal adaptive development of the S/SF filter, suitable for realtime and on-a-chip implementation, has been designed in . However, to significantly suppress time requirements of the space/spatial-frequency-based systems, the graphic processing units (GPUs)-based implementation of these systems can be considered as the possible solution. In this paper, the RTL design methodology-based solution from  is compared with the corresponding GPUs-based solutions.
The goal of this paper is to propose a synthesis based design methodology for communication interfaces at transaction level. This methodology can guarantee the synthesizability of high level communications when IP cores each use a different type of communication structure. It also supports changes in design interface in case of IP core changes. The other benefit of the proposed methodology is the ability to manage different kinds of protocols at both sides of the channel. The focus of the paper is on one-to-one communications and other types of communication channels are not discussed in this work.
In this paper, a design methodology for toroid-type superconducting magnetic energy storage system using the analytical method and data table from finite element analysis is proposed. The method simplifies the model, and uses analytically derived equations to calculate the energy and center flux density. In order to determine the number of turns and current using the analytic process, perpendicular flux density and parallel flux density are obtained from the data table. A 2.5-MJ toroid-type superconducting magnetic energy storage system is designed using the proposed method.
This guide will have chapters dealing with structural loadings, subsurface investigations and the design of spread footing type foundations, drilled shafts, piles, anchors and load tests.
This standard defines the property specification language (PSL), which formally describes electronic system behavior. This standard specifies the syntax and semantics for PSL and also clarifies how PSL interfaces with various standard electronic system design languages.