Conferences related to Compressive stress

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2021 IEEE Photovoltaic Specialists Conference (PVSC)

Photovoltaic materials, devices, systems and related science and technology


2020 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC)

The conference program will consist of plenary lectures, symposia, workshops and invitedsessions of the latest significant findings and developments in all the major fields of biomedical engineering.Submitted papers will be peer reviewed. Accepted high quality papers will be presented in oral and postersessions, will appear in the Conference Proceedings and will be indexed in PubMed/MEDLINE


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.


2020 IEEE International Conference on Plasma Science (ICOPS)

IEEE International Conference on Plasma Science (ICOPS) is an annual conference coordinated by the Plasma Science and Application Committee (PSAC) of the IEEE Nuclear & Plasma Sciences Society.


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Periodicals related to Compressive stress

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Advanced Packaging, IEEE Transactions on

The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.


Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Biomedical Engineering, IEEE Transactions on

Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.


Components and Packaging Technologies, IEEE Transactions on

Component parts, hybrid microelectronics, materials, packaging techniques, and manufacturing technology.


Computer Graphics and Applications, IEEE

IEEE Computer Graphics and Applications (CG&A) bridges the theory and practice of computer graphics. From specific algorithms to full system implementations, CG&A offers a strong combination of peer-reviewed feature articles and refereed departments, including news and product announcements. Special Applications sidebars relate research stories to commercial development. Cover stories focus on creative applications of the technology by an artist or ...


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Most published Xplore authors for Compressive stress

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Xplore Articles related to Compressive stress

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Deep submergence photographic port

1970 IEEE International Conference on Engineering in the Ocean Environment - Digest of Technical Papers, 1970

None


Magnetostriction of TbDy Single Crystals Under Compressive Stress

1990 IEEE International Magnetics Conference (INTERMAG), 1990

None


Exploring the limits of stress-enhanced hole mobility

IEEE Electron Device Letters, 2005

Hole mobility is found to more than double in fabricated p-MOSFETs with SiGe source/drain due to longitudinal compressive stress in the channel exceeding 1 GPa. The maximum observed low-field mobility enhancement is 140% at a simulated stress level of 1.45 GPa. The mobility enhancement is approximately linear with stress at moderate levels but becomes super-linear above 1 GPa. An important ...


Holographic deformation analysis of the human femur

2001 Conference Proceedings of the 23rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2001

The deformations of the neck and head of the human dried femur were measured and analyzed with loads applied at the femoral head. Particular attention was paid to measurements of bones with osteoporosis. We used double exposures or real-time holographic interferometry to measure precisely. The distal part of each femur was embedded in super hard plaster, and the load was ...


Enhancement of CMOS performance by process-induced stress

IEEE Transactions on Semiconductor Manufacturing, 2005

A detailed analysis of the process-induced stress during a standard CMOS manufacturing is presented. Dependence of transistor performance on layout is attributed to the combination of stress induced by shallow trench isolation and source/drain (S/D) silicide. Based on the layout sensitivity, the effect of an individual stress component on NMOS and PMOS is identified. The optimization of transistor layout is ...


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Educational Resources on Compressive stress

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IEEE-USA E-Books

  • Deep submergence photographic port

    None

  • Magnetostriction of TbDy Single Crystals Under Compressive Stress

    None

  • Exploring the limits of stress-enhanced hole mobility

    Hole mobility is found to more than double in fabricated p-MOSFETs with SiGe source/drain due to longitudinal compressive stress in the channel exceeding 1 GPa. The maximum observed low-field mobility enhancement is 140% at a simulated stress level of 1.45 GPa. The mobility enhancement is approximately linear with stress at moderate levels but becomes super-linear above 1 GPa. An important consequence of this behavior is that for moderate stress levels, an average channel stress can be used to estimate the performance of transistors with a nonuniform stress distribution across the channel width. Two alternative approaches to model stress-enhanced hole mobility are suggested. Analysis of the physical effects behind the experimental observations reveals the relative roles of band repopulation and mass modulation. In addition, previously published wafer bending experiments with compressive stress levels below 400 MPa are used to implicitly verify the accuracy of the stress simulations.

  • Holographic deformation analysis of the human femur

    The deformations of the neck and head of the human dried femur were measured and analyzed with loads applied at the femoral head. Particular attention was paid to measurements of bones with osteoporosis. We used double exposures or real-time holographic interferometry to measure precisely. The distal part of each femur was embedded in super hard plaster, and the load was applied at the femoral head. In order to better simulate the situation of a femur under physiological muscles, we used the 3D finite element method (FEM) for our analyses. After modeling the femur, which consisted of meshing as eight noded elements for each section of diaphysis, we used the 3D FEM to calculate stress and strain. We obtained the following results : (1)the deformations increased with the progress of osteoporosis;(2) femur with osteoporosis showed obvious rotational components in the femoral shaft and (3) a compressive stress distribution could be found at the medial side of the diaphyseal region by using the FEM.

  • Enhancement of CMOS performance by process-induced stress

    A detailed analysis of the process-induced stress during a standard CMOS manufacturing is presented. Dependence of transistor performance on layout is attributed to the combination of stress induced by shallow trench isolation and source/drain (S/D) silicide. Based on the layout sensitivity, the effect of an individual stress component on NMOS and PMOS is identified. The optimization of transistor layout is proposed to improve the CMOS performance.

  • STI Effect on Flicker Noise in 0.13-μm RF NMOS

    This paper reports the effect of shallow-trench-isolation (STI) on generation- recombination (G-R) noise and flicker noise variation in 0.13-μm RF MOSFETs for the first time. The devices with relatively small finger widths (W = 1 μm/Nfinger= 40 and W= 5 μm/Nfinger= 8) presented more pronounced G-R noise compared to those with W= 10 mum/Nfinger= 4 devices. In addition, a wide variation of noise levels was observed for devices with smaller finger widths and more finger numbers. The results can be explained by the effect of STI, which affects the carrier mobility due to the compressive stress, also generates traps at the edge of STI region resulting in G-R noise. Moreover, the metals employed in 0.13-μm CMOS technology, Cu and Co, may also be responsible for the G-R noise observed in the devices.

  • Magnetostriction in FeTaN thin films

    Magnetostriction is studied in FeTaN single layer thin films deposited by high power density, high growth rate, DC magnetron sputtering. Magnetostriction is found to increase linearly with the nitrogen content of the films, passing from negative to positive with increasing nitrogen content. Thinner films exhibit larger positive magnetostriction than thicker films deposited at the same nitrogen flow rate. Film stress is found to be tensile in as-deposited films grown at zero nitrogen pressure. As the nitrogen content in the films increases, the film stress changes from tensile to compressive and increases in magnitude, while annealing at 300 degrees C reduces the magnitude of film stress without affecting magnetostriction. Stress anisotropy is found to reach a minimum at low nitrogen flow rate, and stripe domain formation accompanies large stress anisotropy at high nitrogen flow rates.<<ETX>>

  • Monte Carlo Stress Engineering of Scaled (110) and (100) Bulk pMOSFETs

    Bulk pMOSFET performance enhancement by combinations of SiGe pockets, compressively stressed cap liner and (110) surface orientation is investigated by mechanical stress and Monte Carlo device simulation. In agreement with recent measurements, the on-current gain by a (110) surface orientation of the 45 nm pMOSFET with a 3 GPa compressive cap liner is 32% and 16% without and with the presence of Si<sub>0.8</sub>Ge<sub>0.2</sub> pockets, respectively. However, the performance enhancement by a (110) surface orientation strongly decreases upon scaling and for increasing liner stress. This suggests that the enhanced mobility for (110) surface orientation may lose its advantage in the limit of further scaling and increasing stress.

  • Stress dependence of the frequency of quartz plates

    The third-order elastic constants of crystalline quartz are used to calculate the stress dependence of the frequency of quartz oscillator plates.

  • FinFET stress engineering using 3D mechanical stress and 2D Monte Carlo device simulation

    A simulation methodology for FinFET stress and crystallographic orientation engineering is introduced and applied to tall scaled p- and n-type FinFETs with strained nitride layers on (001) wafers. The methodology consists of combining 3D mechanical stress simulation with 2D Monte Carlo device simulation where an averaged channel stress tensor is used. 50 nm down to 10 nm gate-length p- and n-type FinFETs with (110)/110 surface and channel orientation as well as (010)/100 n-type FinFETs are simulated with compressively and tensile strained cap layers, respectively, where liner stress values from 0.8 to 2.0 GPa are considered. Stress-induced Idsat gains in the range of 10 to 35% are found for pFinFETs with increasing tendency upon scaling, while the nFinFETs involve gains between 5 and 15% decreasing for smaller gate lengths with the highest absolute current being obtained for the 100 channel direction.



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