Conferences related to Combinational circuits

Back to Top

2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE International Conference on Systems, Man, and Cybernetics (SMC)

The 2020 IEEE International Conference on Systems, Man, and Cybernetics (SMC 2020) will be held in Metro Toronto Convention Centre (MTCC), Toronto, Ontario, Canada. SMC 2020 is the flagship conference of the IEEE Systems, Man, and Cybernetics Society. It provides an international forum for researchers and practitioners to report most recent innovations and developments, summarize state-of-the-art, and exchange ideas and advances in all aspects of systems science and engineering, human machine systems, and cybernetics. Advances in these fields have increasing importance in the creation of intelligent environments involving technologies interacting with humans to provide an enriching experience and thereby improve quality of life. Papers related to the conference theme are solicited, including theories, methodologies, and emerging applications. Contributions to theory and practice, including but not limited to the following technical areas, are invited.


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)

The program of the conference will be tailored to reflect the wide spectrum of topics and research interest shared among the organizing entities. This collaboration will be oriented towards advanced research in adaptive systems which constitutes the highlights of the NEWCAS conference, but also areas related to analog and digital signal processing, low power consumption, and circuits and systems designs. The topics include, but are not limited to: Computer architecture and memories, Analog circuit design, Digital and mixed-signal circuit design, RF circuit design, mm-Wave circuits, Microsystems, sensors and actuators, Test and verification, Communication, microwaves and RF, Technology Trends, Data and signal processing, Neural networks and artificial vision, CAD and design tools, Low-Power circ. & syst. techniques, Imaging & image sensors, Embedded hand-held devices, Biomed. circuits & systems, Energy Harvesting / Scavenging

  • 2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)

    NEWCAS2018 will encompass a wide range of special sessions and keynote talks given by prominent expertscovering key areas of research in microsystems in order to provide all attendees a unique forum for the exchange of ideas and results. The program of the conference will be tailored to reflect the wide spectrum of topics and research interest shared by researchers in this field.

  • 2017 15th IEEE International New Circuits and Systems Conference (NEWCAS)

    IEEE International NEWCAS Conference is tailored to reflect the wide spectrum of topics and research interests shared among the organizing entities. This collaboration will be oriented towards advanced research and development activities from academia, research institutions, and industry. Topics include, but are not limited to analog, mixed-signal, and digital integrated circuits and systems, radio-frequency circuits, computer architecture and memories, microsystems, sensors and actuators, test and verification, telecommunication, technology trends, power and energy circuits and systems, biomedical circuits, energy harvesting, computer-aided design tools, device modeling, and embedded portable devices.

  • 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS)

    IEEE International NEWCAS Conference is tailored to reflect the wide spectrum of topics and research interests shared among the organizing entities. This collaboration will be oriented towards advanced research and development activities from academia, research institutions, and industry. Topics include, but are not limited to analog, mixed-signal, and digital integrated circuits and systems, radio-frequqncy circuits, computer architecture and memories, microsystems, sensors and actuators, test and verification, telecommunication, technology trends, power and energy circuits and systems, biomedical circuits, energy harvesting, computer-aided design tools, and embedded portable devices.

  • 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)

    The program of the conference will be tailored to reflect the wide spectrum of topics and research interest shared among the organizing entities. This collaboration will be oriented towards advanced research in adaptive systems which constitutes the highlights of the NEWCAS conference, but also areas related to analog and digital signal processing, low power consumption, and circuits and systems designs. The topics include, but are not limited to: Computer architecture and memories, Analog circuit design, Digital and mixed-signal circuit design, RF circuit design, Microsystems, sensors and actuators, Test and verification, Telecom, microwaves and RF, Technology Trends, Data and signal processing, Neural networks and artificial vision, CAD and design tools, Low-Power circ. & syst. techniques, Imaging & image sensors, Embedded hand-held devices, Biomed. circuits & systems, Energy Harvesting / Scavenging

  • 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)

    will encompass a wide range of special sessions and keynote talks given by prominent experts covering key areas of research in microsystems in order to provide all attendees a unique forum for the exchange of ideas and results. The program of the conference will be tailored to reflect the wide spectrum of topics and research interest shared by researchers in this field.

  • 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)

    NEWCAS is a major international conference presenting design methodologies, techniques and experimental results in emerging electronics, circuits and systems topics. The NEWCAS conference deals with analog and digital signal processing, low power consumption, circuits and systems design.

  • 2012 IEEE 10th International New Circuits and Systems Conference (NEWCAS)

    The conference will include regular and special session on emerging electronic systems and design methods, plenary sessions on selected advanced aspects of the theory, design and applications of electronic systems, as well as tutorials given by experts on specific topics.

  • 2011 IEEE 9th International New Circuits and Systems Conference (NEWCAS)

    NEWCAS is a major international conference presenting design methodologies, techniques and experimental results in emerging electronics, circuits and systems topics. The NEWCAS conference deals with analog and digital signal processing, low power consumption, circuits and systems design.

  • 2010 8th IEEE International NEWCAS Conference (NEWCAS)

    The conference will include regular and special session on emerging electronic systems and design methods, plenary sessions on selected advanced aspects of the theory, design and applications of electronic systems, as well as tutorials given by experts on specific topics.

  • 2009 Joint IEEE North-East Workshop on Circuits and Systems (NEWCAS) and TAISA Conference (NEWCAS-TAISA 2009)

    Advance in microelectronics in addition to signal analog processing, and their applications to telecommunications, artificial vision and biomedical. This include: system architectures, circuit (digital, analog and mixed) and system-level design, test and verification, data and signal processing, microsystems, memories and sensors and associated analog processing, mathematical methods and design tools.

  • 2008 Joint IEEE North-East Workshop on Circuits and Systems (NEWCAS) and TAISA Conference (NEWCAS-TAISA 2008)

    Advanced research in microelectronics and microsystems constitutes the highlights of the NEWCAS conferences in addition to topics regarding analog data and signal processing and their applications well-established in the TAISA conferences.

  • 2006 IEEE North-East Workshop on Circuits and Systems (NEWCAS 2006)

  • 2005 IEEE North-East Workshop on Circuits and Systems (NEWCAS 2005)

  • 2004 IEEE North-East Workshop on Circuits and Systems (NEWCAS 2004)


2019 24th Asia and South Pacific Design Automation Conference (ASP-DAC)

ASP-DAC 2019 is the twenty-second annual international conference on VLSI design automation in Asia and South Pacific region, one of the most active regions of design and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC.


More Conferences

Periodicals related to Combinational circuits

Back to Top

Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Design & Test of Computers, IEEE

IEEE Design & Test of Computers offers original works describing the methods used to design and test electronic product hardware and supportive software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. Topics include IC/module design, low-power design, electronic design automation, design/test verification, practical technology, and standards. IEEE Design & Test of ...


Education, IEEE Transactions on

Educational methods, technology, and programs; history of technology; impact of evolving research on education.


More Periodicals

Most published Xplore authors for Combinational circuits

Back to Top

Xplore Articles related to Combinational circuits

Back to Top

Stress testing FET gates without the use of test patterns

1975 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1975

This paper will cover a technique for stressing of all FET gates in LSI dynamic random logic FET circuits. This is accomplished by reversing the sequence of the clock signals. No input test patterns are required.


Circuit based quantification: back to state set manipulation within unbounded model checking

Design, Automation and Test in Europe, 2005

A non-canonical circuit-based state set representation is used to perform quantifier elimination efficiently. The novelty of this approach lies in adapting equivalence checking and logic synthesis techniques to the goal of compacting circuit based state set representations resulting from existential quantification. The method can be efficiently combined with other verification approaches such as inductive and SAT-based pre-image verifications.


Fault detection and diagnosis of k-UCP circuits under totally observable condition

[1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium, 1990

A method is presented for detecting stuck-open faults, as well as stuck-at faults, in CMOS combinational circuits by short test sequences of fixed length. The discussion is based on the assumption that outputs of all the gates in a circuit are observable. This assumption will become reasonable when a new testability solution called CrossCheck, or a new test equipment, called ...


Extended binary nonlinear codes and their application in testing and compression

2017 22nd IEEE European Test Symposium (ETS), 2017

In this paper, we show that the binary linear codes can be extended by a relatively big number of check bits in such a way that the code words preserve the value of a maximum number of independently specified bits from the original linear code words. It can improve pattern compression and-or pseudo- exhaustive testing. Existing linear compression and testing ...


Majority Gate Based Design for Combinational Quantum Cellular Automata (QCA) Circuits

2008 40th Southeastern Symposium on System Theory (SSST), 2008

Quantum cellular automata (QCA) present an important nanotechnology paradigm to design digital logic. A cell consists of four quantum dots located at the corners of a square. This paper considers the design of complex logic blocks using a fundamental QCA device, which is a three input majority logic gate. Our technique uses the 'disjointing concept', commonly used in the reliability ...


More Xplore Articles

Educational Resources on Combinational circuits

Back to Top

IEEE-USA E-Books

  • Stress testing FET gates without the use of test patterns

    This paper will cover a technique for stressing of all FET gates in LSI dynamic random logic FET circuits. This is accomplished by reversing the sequence of the clock signals. No input test patterns are required.

  • Circuit based quantification: back to state set manipulation within unbounded model checking

    A non-canonical circuit-based state set representation is used to perform quantifier elimination efficiently. The novelty of this approach lies in adapting equivalence checking and logic synthesis techniques to the goal of compacting circuit based state set representations resulting from existential quantification. The method can be efficiently combined with other verification approaches such as inductive and SAT-based pre-image verifications.

  • Fault detection and diagnosis of k-UCP circuits under totally observable condition

    A method is presented for detecting stuck-open faults, as well as stuck-at faults, in CMOS combinational circuits by short test sequences of fixed length. The discussion is based on the assumption that outputs of all the gates in a circuit are observable. This assumption will become reasonable when a new testability solution called CrossCheck, or a new test equipment, called on electron-beam tester, is used. The concept of k-UCP (uniform, having a (k+1)-Color solution and compatible polarity) circuits is introduced, and it is shown that 2(k+1) kinds of test sequences of length k(k+1)+1 are sufficient to detect stuck-open faults, as well as stuck-at faults in a k-UCP circuit. Furthermore, it is shown that single stuck-open faults can be located by using a fault diagnosis table. A method which can speed up the generation of a fault diagnosis table is also proposed.<<ETX>>

  • Extended binary nonlinear codes and their application in testing and compression

    In this paper, we show that the binary linear codes can be extended by a relatively big number of check bits in such a way that the code words preserve the value of a maximum number of independently specified bits from the original linear code words. It can improve pattern compression and-or pseudo- exhaustive testing. Existing linear compression and testing techniques adopt linear codes either for pattern expansion in the decompressor or for pattern generation. The minimum code distance of the dual linear code determines the encoding efficiency, the greater distance causes the bigger maximum number of independently specified bits on the decompressor outputs. While keeping the number of specified bits for longer code words the extended codes provide a possibility of feeding more parallel scan chains with the decompressor output bits. In the case of pseudo-exhaustive test pattern generators, the extended nonlinear codes guarantee an existence of the universal pseudo-exhaustive test set with better parameters than can be obtained for linear test pattern generators. We compare the properties of the extended non-linear and linear codes and demonstrate the effectiveness of the decompressors using these codes.

  • Majority Gate Based Design for Combinational Quantum Cellular Automata (QCA) Circuits

    Quantum cellular automata (QCA) present an important nanotechnology paradigm to design digital logic. A cell consists of four quantum dots located at the corners of a square. This paper considers the design of complex logic blocks using a fundamental QCA device, which is a three input majority logic gate. Our technique uses the 'disjointing concept', commonly used in the reliability literature. Our comparison with two existing approaches shows that the proposed method provides an efficient solution.

  • Identification of strong (weak) complete sets of logic primitives and their application in the realization of arbitrary switching functions

    A method for the identification of strong (weak) complete sets of logic primitives and their application in the realization of arbitrary combinational switching functions are presented. Two computer programs are discussed. The first program takes as input the given combinational switching function or the set and tests it for a strong (weak) complete function or set. The same program tests the function or the set to determine whether it can form the strong (weak) basis. The second program can be used to realize any arbitrary switching function using the given function if it happens to be a strong complete function known from the first program.<<ETX>>

  • Exact calculation of synchronization sequences based on binary decision diagrams

    A synchronization sequence for a synchronous design D is a sequence of primary input vectors which when applied to any initial state of D will drive D to a single state, called a reset state. The authors present efficient methods based upon the universal alignment theorem and binary decision diagrams to compute a synchronization sequence, to compute a tight lower bound for the length of such a sequence, and to check that an initial state given in the specification is a reset state. It was shown in the experiments that the proposed method can handle fairly large circuits and the length of the actual synchronization sequence computed is quite close to the lower bound.<<ETX>>

  • A generic TC-based method to find the weakness in different phases of masking schemes

    Masking is one of the most commonly used Side-Channel Attack (SCA) countermeasures and is built on a security framework, such as the ISW framework, and ensures theoretical security through secret sharing. Unfortunately, the theoretical security cannot guarantee practical security, because several possible weaknesses may exist in the actual implementation. These weaknesses likely come from the masking schemes or are introduced by the implementation methods. Finding the possible weakness of the masking scheme is an interesting and important issue for real applications. In this paper, the possible weaknesses for masking schemes in Field-Programmable Gate Array (FPGA) design are discussed. It was found that the combinational circuit is the key to the security of masking schemes. The Toggle Count (TC) method and its extension are utilized to evaluate the security of masking schemes in the design phase and the implementation phase separately. Comparing different logic-level simulators for the Xilinx FPGA platform, the behavioral and post- translate simulations are considered as the analysis method in the design phase, while the post-map and the post-route simulations are used to find the weakness during the implementation phase. Moreover, a Standard Delay Format (SDF) based improvement scheme is proposed to significantly increase the effectiveness of the TC model.

  • Robust testing for stuck-at faults

    This paper proposes a generalization of robust tests with respect to assumptions about fault models and circuit models. The specific case of d-robust tests for single stuck-at faults is studied. These tests maintain their validity in the presence of macro-delay faults. A macro-delay of size n means that the delay of all combinational paths can be in the range [O,nT] where T is the clock period. We give a simple method of duplicating a test vector n times to produce a d-robust test for a stuck-at fault in a combinational circuit. We further implement a more complex algorithm to derive d-robust tests for stuck-at faults in sequential circuits.

  • Design of multiple-valued linear digital circuits for highly parallel k-ary operations

    To design highly parallel digital circuits such as an adder and a multiplier, it is difficult to find the optimal code assignment in the nonlinear digital system. On the other hand, the use of the linear concept in digital systems seems to be very attractive because analytical methods can be utilized. For unary operations, the design method of locally computable circuits have been discussed. In this paper, we propose a new design method of highly parallel multiple-valued linear digital circuits for k-ary operations using the concept of identification of input-output graphs by the introduction of multiplicated redundant symbols.<<ETX>>



Standards related to Combinational circuits

Back to Top

No standards are currently tagged "Combinational circuits"


Jobs related to Combinational circuits

Back to Top