Conferences related to Memory

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2020 IEEE/ASME International Conference on Advanced Intelligent Mechatronics (AIM)

The scope of the 2020 IEEE/ASME AIM includes the following topics: Actuators, Automotive Systems, Bioengineering, Data Storage Systems, Electronic Packaging, Fault Diagnosis, Human-Machine Interfaces, Industry Applications, Information Technology, Intelligent Systems, Machine Vision, Manufacturing, Micro-Electro-Mechanical Systems, Micro/Nano Technology, Modeling and Design, System Identification and Adaptive Control, Motion Control, Vibration and Noise Control, Neural and Fuzzy Control, Opto-Electronic Systems, Optomechatronics, Prototyping, Real-Time and Hardware-in-the-Loop Simulation, Robotics, Sensors, System Integration, Transportation Systems, Smart Materials and Structures, Energy Harvesting and other frontier fields.


2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2019 IEEE International Conference on Image Processing (ICIP)

The International Conference on Image Processing (ICIP), sponsored by the IEEE SignalProcessing Society, is the premier forum for the presentation of technological advances andresearch results in the fields of theoretical, experimental, and applied image and videoprocessing. ICIP 2019, the 26th in the series that has been held annually since 1994, bringstogether leading engineers and scientists in image and video processing from around the world.


2019 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2019 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges.


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Periodicals related to Memory

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Antennas and Propagation, IEEE Transactions on

Experimental and theoretical advances in antennas including design and development, and in the propagation of electromagnetic waves including scattering, diffraction and interaction with continuous media; and applications pertinent to antennas and propagation, such as remote sensing, applied optics, and millimeter and submillimeter wave techniques.


Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Audio, Speech, and Language Processing, IEEE Transactions on

Speech analysis, synthesis, coding speech recognition, speaker recognition, language modeling, speech production and perception, speech enhancement. In audio, transducers, room acoustics, active sound control, human audition, analysis/synthesis/coding of music, and consumer audio. (8) (IEEE Guide for Authors) The scope for the proposed transactions includes SPEECH PROCESSING - Transmission and storage of Speech signals; speech coding; speech enhancement and noise reduction; ...


Automatic Control, IEEE Transactions on

The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


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Xplore Articles related to Memory

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A Cu<inf>x</inf>O-based resistive memory with low power and high reliability for SOC nonvolatile memory applications

2010 IEEE International Memory Workshop, 2010

A CuxO-based resistive memory is successfully integrated in 0.13 μm logic process. Operation algorithm is optimized to achieve low power consumption with reset current down to 30 μA. High thermal stability and small cell size less than 22 F2have been demonstrated. The advantages make this device promising for system on chip non-volatile memory applications.


A 90nm 32-mb phase change memory with flash SPI compatibility

2014 IEEE 6th International Memory Workshop (IMW), 2014

A 32-Mb Phase Change Memory is realized in a 90nm 6-Metal process. An erase speed of 10.0-Mb/second and program speed of 35.6-Mb/second is achieved. The cell retention is interpolated to be 10 years at 85°C and cell endurance is measured to be 109cycles. The 25F2mushroom cell phase change memory utilizes a planar transistor. An ECC solution is employed to correct ...


Modeling and Characterization of Program / Erasure Speed and Retention of TiN-gate MANOS (Si-Oxide-SiNx-Al2O3-Metal Gate) Cells for NAND Flash Memory

2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop, 2007

In this study, physical properties of different trapping nitrides were extracted, and the program efficiency of MANOS cell was explained. We also showed shallow traps were generated at trapping nitride by etching damage, and this could be cured resulting great improvement of cell performance. Lastly, erasure mechanism of TiN-gate MANOS cell was discussed with some experimental and modeling results.


3-dimensional analysis on the cell string current of NAND flash memory

Symposium Non-Volatile Memory Technology 2005., 2005

The cell string current of NAND flash memory is very small due to large resistance from the cells connected in series. In this paper, scaling effects on the cell current are analyzed for 70/60/50 nm NAND flash technologies using 3-dimensional TCAD simulation. The geometrical and process parameters are varied and their effects are quantified. It is identified that the coupling ...


Vertical cross-point resistance change memory for ultra-high density non-volatile memory applications

2009 Symposium on VLSI Technology, 2009

Vertically defined resistance change memory cells for the vertical cross-point architecture (VCPA) as a high density non-volatile memory application are successfully demonstrated with a NiO switching layer. They showed both unipolar and bipolar switching mode. Several issues in realization for VCPA and their possible solutions are discussed.


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Educational Resources on Memory

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IEEE.tv Videos

Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
High-Bandwidth Memory Interface Design
Erasing Logic-Memory Boundaries in Superconductor Electronics - Vasili Semenov: 2016 International Conference on Rebooting Computing
IRDS: Lithography - Mark Neisser at INC 2019
The Memory of Cars Talk by Tom Coughlin
From Edge To Core: Memory-Driven Hardware and Software Co-Design - IEEE Rebooting Computing Industry Summit 2017
IEEE Medal of Honor Recipient (2009): Dr. Robert Dennard
IRDS: More Moore Outbrief - Mustafa Badaroglu at INC 2019
IMS 2011 Microapps - Memory Effects in RF Circuits: Definition, Manifestations and Fast, Accurate Simulation
Spin Dynamics in Inhomogeneously Magnetized Systems - Teruo Ono: IEEE Magnetics Society Distinguished Lecture 2016
Ted Berger: Far Futures Panel - Technologies for Increasing Human Memory - TTM 2018
Improved Deep Neural Network Hardware Accelerators Based on Non-Volatile-Memory: the Local Gains Technique: IEEE Rebooting Computing 2017
The Superstrider Architecture: Integrating Logic and Memory towards non-von Neumann Computing: IEEE Rebooting Computing 2017
Impact of Linearity and Write Noise of Analog Resistive Memory: IEEE Rebooting Computing 2017
Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip - Anirudh Jain - ICRC 2018
2015 IEEE Honors: IEEE Richard W. Hamming Medal - Imre Csiszar
Array storing and retrieval
Robotics History: Narratives and Networks Oral Histories: Barbara Hayes Roth
How Analytics Measure Up In Fog Environments - Panel Discussion - Fog World Congress 2017
Memory Centric Artificial Intelligence - Damien Querlioz at INC 2019

IEEE-USA E-Books

  • A Cu<inf>x</inf>O-based resistive memory with low power and high reliability for SOC nonvolatile memory applications

    A CuxO-based resistive memory is successfully integrated in 0.13 μm logic process. Operation algorithm is optimized to achieve low power consumption with reset current down to 30 μA. High thermal stability and small cell size less than 22 F2have been demonstrated. The advantages make this device promising for system on chip non-volatile memory applications.

  • A 90nm 32-mb phase change memory with flash SPI compatibility

    A 32-Mb Phase Change Memory is realized in a 90nm 6-Metal process. An erase speed of 10.0-Mb/second and program speed of 35.6-Mb/second is achieved. The cell retention is interpolated to be 10 years at 85°C and cell endurance is measured to be 109cycles. The 25F2mushroom cell phase change memory utilizes a planar transistor. An ECC solution is employed to correct two bits out of a 128-bit data bus, with a 12% chip area overhead. The part is compliant with an SPI spec used for a NOR flash part. Word and bit redundancy are used for repairing defective bits. Fuse information is stored in PCM elements using a technique that increases the reliability of the fuse information, enabling it to withstand a solder cycle. A method is used to ensure proper fuse download at power up, even with the asynchronous power on behavior. Power islands are developed to disable both the high voltage supply needed for writes and peripheral logic needed for the datapath when in a standby mode, thereby reducing standby current.

  • Modeling and Characterization of Program / Erasure Speed and Retention of TiN-gate MANOS (Si-Oxide-SiNx-Al2O3-Metal Gate) Cells for NAND Flash Memory

    In this study, physical properties of different trapping nitrides were extracted, and the program efficiency of MANOS cell was explained. We also showed shallow traps were generated at trapping nitride by etching damage, and this could be cured resulting great improvement of cell performance. Lastly, erasure mechanism of TiN-gate MANOS cell was discussed with some experimental and modeling results.

  • 3-dimensional analysis on the cell string current of NAND flash memory

    The cell string current of NAND flash memory is very small due to large resistance from the cells connected in series. In this paper, scaling effects on the cell current are analyzed for 70/60/50 nm NAND flash technologies using 3-dimensional TCAD simulation. The geometrical and process parameters are varied and their effects are quantified. It is identified that the coupling ratio has the most significant impact on the cell current and the LDD engineering is more relevant for higher cell current

  • Vertical cross-point resistance change memory for ultra-high density non-volatile memory applications

    Vertically defined resistance change memory cells for the vertical cross-point architecture (VCPA) as a high density non-volatile memory application are successfully demonstrated with a NiO switching layer. They showed both unipolar and bipolar switching mode. Several issues in realization for VCPA and their possible solutions are discussed.

  • A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology

    The first multi-layer stacked 3D Flash memory was proposed as BiCS FLASH in 2007 [1]. Since then, memory bit density has grown rapidly due to the increase in the number of stacked layers from continuous 3D technology innovations. On the other hand, the multi-level-cell technology, which was initially proposed for 2D Flash, has also been adopted to 3D Flash memories. The first 3b/cell 32-layer Flash was presented in 2015 [2], followed by a 48-layer one in 2016 [3], and a 64-layer one in 2017 [4,5]. This paper describes a 512Gb 3b/cell 3D Flash memory in a 96-word-line-layer BiCS FLASH technology. This work implements three key technologies to improve performance: (1) a string based start bias control scheme achieves a 7% shorter program time; (2) a smart V<sub>t</sub>-tracking read improves read retry performance by minimizing the tracking time and supporting a program suspend read function, and; (3) a low- pre-charge sense-amplifier bus scheme reduces both the power consumption and the data-transfer time between the sense amplifier (SA) and the data cache by half. Figure 20.1.1 shows the die micrograph and the summary of the key features of the chip.

  • A 0.18-/spl mu/m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)

    A nonvolatile 64-Mb 1T1R phase-transition random access memory (PRAM) has been developed by fully integrating chalcogenied storage material (GST: Ge/sub 2/Sb/sub 2/Te/sub 5/) into 0.18-/spl mu/m CMOS technology. To optimize SET/RESET distribution, 512-kb sub-array core architecture was proposed, featuring meshed ground line and separated SET/RESET control schemes. Random read access time, random SET and RESET write access times were measured to be 60 ns, 120 ns, and 50 ns, respectively, at 3.0-V supply voltage with 30/spl deg/ C.

  • A 70nm 16Gb 16-level-cell NAND Flash Memory

    A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed. This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash with the same design rule. New programming method achieves 0.62 MB/s programming throughput.

  • Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory

    Vertical NAND flash memory cell array by TCAT (terabit cell array transistor) technology is proposed. Damascened metal gate SONOS type cell in the vertical NAND flash string is realized by a unique dasiagate replacementpsila process. Also, conventional bulk erase operation of the cell is successfully demonstrated. All advantages of TCAT flash is achieved without any sacrifice of bit cost scalability.

  • High-performance 1-Gb-NAND flash memory with 0.12-/spl mu/m technology

    A 1.8-V, 1-Gb NAND flash memory is fabricated with 0.12-/spl mu/m CMOS STI process technology. For higher integration, a 32-cell NAND structure, which enables row decoder layout in one block pitch, is applied for the first time. Resulting cell and die sizes are 0.076 /spl mu/m/sup 2/ and 129.6 mm/sup 2/, respectively. A pseudo-4-phase charge pump circuit can generate up to 20 V even under the supply voltage of 1.6 V. A newly applied cache program function and expanded page size of (2 k + 64) byte lead to program throughput of 7 MB/s. The page copy-back function is provided for on-chip garbage collection. The read throughput of 27 MB/s is achieved by simply expanding I/O width and page size. A measured disturbance free-window of 3.5 V at 1.5 V-V/sub DD/ is obtained.



Standards related to Memory

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IEEE Standard for Authenticated Encryption with Length Expansion for Storage Devices

This standard specifies requirements for cryptographic units that provide encryption and authentication for data contained within storage media. Full interchange requires additional format specifications (such as compression algorithms and physical data format) that are beyond the scope of this standard.


IEEE Standard for Communicating Among Processors and Peripherals Using Shared Memory (Direct Memory Access - DMA)


IEEE Standard for Cryptographic Protection of Data on Block-Oriented Storage Devices

This standard specifies elements of an architecture for cryptographic protection of data on block-oriented storage devices, describing the methods, algorithms, and modes of data protection to be used.


IEEE Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface (SCI) Signaling Technology (RamLink)

Define a high-bandwidth interface that will permit access to the large internal bandwidth already available in dynamic memory chips. The goal is to increase the performance and reduce the complexity of memory systems by using a subset of SCI protocols. Hierarchical memory systems will be considered, from multi-level caches to main-memory systems. The interface specification will apply to individual memory ...


IEEE Standard for Scalable Storage Interface

This standard defines a scalable interface for use with memory-mapped storage units and other devices. The term storage unit" can encompass rotating


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