Conferences related to Benchmark testing

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2023 Annual International Conference of the IEEE Engineering in Medicine & Biology Conference (EMBC)

The conference program will consist of plenary lectures, symposia, workshops and invitedsessions of the latest significant findings and developments in all the major fields of biomedical engineering.Submitted full papers will be peer reviewed. Accepted high quality papers will be presented in oral and poster sessions,will appear in the Conference Proceedings and will be indexed in PubMed/MEDLINE.


2021 IEEE Photovoltaic Specialists Conference (PVSC)

Photovoltaic materials, devices, systems and related science and technology


2020 IEEE International Symposium on Antennas and Propagation and North American Radio Science Meeting

The joint meeting is intended to provide an international forum for the exchange of information on state of the art research in the area of antennas and propagation, electromagnetic engineering and radio science


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

CVPR is the premier annual computer vision event comprising the main conference and several co-located workshops and short courses. With its high quality and low cost, it provides an exceptional value for students, academics and industry researchers.

  • 2019 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premier annual computer vision event comprising the main conference and severalco-located workshops and short courses. With its high quality and low cost, it provides anexceptional value for students, academics and industry researchers.

  • 2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premier annual computer vision event comprising the main conference and several co-located workshops and short courses. With its high quality and low cost, it provides an exceptional value for students, academics and industry researchers.

  • 2017 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premiere annual Computer Vision event comprising the main CVPR conferenceand 27co-located workshops and short courses. With its high quality and low cost, it provides anexceptional value for students,academics and industry.

  • 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premiere annual Computer Vision event comprising the main CVPR conference and 27 co-located workshops and short courses. With its high quality and low cost, it provides an exceptional value for students, academics and industry.

  • 2015 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    computer, vision, pattern, cvpr, machine, learning

  • 2014 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premiere annual Computer Vision event comprising the main CVPR conference and 27 co-located workshops and short courses. Main conference plus 50 workshop only attendees and approximately 50 exhibitors and volunteers.

  • 2013 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premiere annual Computer Vision event comprising the main CVPR conference and 27 co-located workshops and short courses. With its high quality and low cost, it provides an exceptional value for students, academics and industry.

  • 2012 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    Topics of interest include all aspects of computer vision and pattern recognition including motion and tracking,stereo, object recognition, object detection, color detection plus many more

  • 2011 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    Sensors Early and Biologically-Biologically-inspired Vision, Color and Texture, Segmentation and Grouping, Computational Photography and Video

  • 2010 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    Concerned with all aspects of computer vision and pattern recognition. Issues of interest include pattern, analysis, image, and video libraries, vision and graphics, motion analysis and physics-based vision.

  • 2009 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    Concerned with all aspects of computer vision and pattern recognition. Issues of interest include pattern, analysis, image, and video libraries, vision and graphics,motion analysis and physics-based vision.

  • 2008 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

  • 2007 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

  • 2006 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

  • 2005 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)


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Periodicals related to Benchmark testing

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Antennas and Propagation, IEEE Transactions on

Experimental and theoretical advances in antennas including design and development, and in the propagation of electromagnetic waves including scattering, diffraction and interaction with continuous media; and applications pertinent to antennas and propagation, such as remote sensing, applied optics, and millimeter and submillimeter wave techniques.


Automation Science and Engineering, IEEE Transactions on

The IEEE Transactions on Automation Sciences and Engineering (T-ASE) publishes fundamental papers on Automation, emphasizing scientific results that advance efficiency, quality, productivity, and reliability. T-ASE encourages interdisciplinary approaches from computer science, control systems, electrical engineering, mathematics, mechanical engineering, operations research, and other fields. We welcome results relevant to industries such as agriculture, biotechnology, healthcare, home automation, maintenance, manufacturing, pharmaceuticals, retail, ...


Biomedical Engineering, IEEE Transactions on

Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.


Communications Letters, IEEE

Covers topics in the scope of IEEE Transactions on Communications but in the form of very brief publication (maximum of 6column lengths, including all diagrams and tables.)


Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...


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Most published Xplore authors for Benchmark testing

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Xplore Articles related to Benchmark testing

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Maximum SNR Transmit Filtering for Decision-Feedback Equalization in Physical Layer Network Coding

SCC 2013; 9th International ITG Conference on Systems, Communication and Coding, 2013

We consider a two-way relaying system employing physical layer network coding (PNC) in channels suffering from frequency-selective fading. In order to mitigate the distortions introduced by the channel, decision-feedback equalization (DFE) is used at the relay node. We introduce transmit filters that generate identical overall channel impulse responses for the links from both source nodes to the relay node, while ...


An Optimized Timing and Control Flow Checker for Hard Real-Time Systems

26th International Conference on Architecture of Computing Systems 2013, 2013

Dependability and safety are important requirements of embedded real-time systems. It is necessary to integrate mechanisms for an early fault detection to enable a potential error recovery before missing a deadline. Additionally, code size is an important concern regarding these systems. In this paper, we present optimization techniques for a timing and control flow checker designed for hard real-time systems. ...


Deadlock Detector and Solver (DDS)

2018 IEEE/ACM 40th International Conference on Software Engineering: Companion (ICSE-Companion), 2018

Deadlock is among the most complex problems affecting the reliability of programs containing multiple, asynchronous threads. When undetected, deadlocks can lead to permanent thread blockage. Current detection methods are typically based on timeout and rollback of computations, resulting in significant delays. This paper presents Deadlock Detector and Solver (DDS), which can quickly detect and resolve circular deadlocks in Java programs. ...


Function Based Benchmarks to Abstract Parallel Hardware and Predict Efficient Code Partitioning

26th International Conference on Architecture of Computing Systems 2013, 2013

To increase the performance of a program, developers have to parallelize their code due to trends in modern hardware development. Since the parallelization of source code is paired with additional programming effort, it is desirable to know if a parallelization would result in an advantage in performance before implementing it. This paper examines the use of benchmarks for estimating the ...


Cache locking optimization in java virtual machine

IEEE Conference Anthology, 2013

Cache plays an important role in multilevel storage system. It can greatly reduce the memory access latency. So the cache hit rate has a significant impact on the performance of the application. Many processors provide cache locking mechanism, which can lock the certain lines in cache. It enables an application to affect the cache replacement decisions under software control. This ...


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Educational Resources on Benchmark testing

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IEEE-USA E-Books

  • Maximum SNR Transmit Filtering for Decision-Feedback Equalization in Physical Layer Network Coding

    We consider a two-way relaying system employing physical layer network coding (PNC) in channels suffering from frequency-selective fading. In order to mitigate the distortions introduced by the channel, decision-feedback equalization (DFE) is used at the relay node. We introduce transmit filters that generate identical overall channel impulse responses for the links from both source nodes to the relay node, while achieving the maximum signal-to- noise ratio (SNR) for zero-forcing DFE and minimum mean-squared error DFE at the relay node. The performance gain of our novel approach is compared against a benchmark filtering scheme which also creates identical channel impulse responses to enable decision-feedback equalization at the relay.

  • An Optimized Timing and Control Flow Checker for Hard Real-Time Systems

    Dependability and safety are important requirements of embedded real-time systems. It is necessary to integrate mechanisms for an early fault detection to enable a potential error recovery before missing a deadline. Additionally, code size is an important concern regarding these systems. In this paper, we present optimization techniques for a timing and control flow checker designed for hard real-time systems. These improvements allow a massive reduction of the required overhead with only slight decreases of the fault detection capabilities. An experimental evaluation shows that the additional memory usage can be minimized by around 30%, while the execution time overhead is even reduced by around 50%. On the other hand, more than 57% of injected faults can still be detected by our technique - at an average detection latency of less than 30 processor cycles.

  • Deadlock Detector and Solver (DDS)

    Deadlock is among the most complex problems affecting the reliability of programs containing multiple, asynchronous threads. When undetected, deadlocks can lead to permanent thread blockage. Current detection methods are typically based on timeout and rollback of computations, resulting in significant delays. This paper presents Deadlock Detector and Solver (DDS), which can quickly detect and resolve circular deadlocks in Java programs. DDS uses a supervisory controller, which monitors program execution and automatically detects deadlocks resulting from hold-and-wait cycles on monitor locks. When a deadlock is detected, DDS uses a preemptive strategy to break the deadlock. Based on our experiments, DDS can in fact resolve deadlocks without significant run-time overhead.

  • Function Based Benchmarks to Abstract Parallel Hardware and Predict Efficient Code Partitioning

    To increase the performance of a program, developers have to parallelize their code due to trends in modern hardware development. Since the parallelization of source code is paired with additional programming effort, it is desirable to know if a parallelization would result in an advantage in performance before implementing it. This paper examines the use of benchmarks for estimating the performance gain looking at the parallelization of Population Based Algorithms (PBAs) like Genetic Algorithms (GAs) and Particle Swarm Optimization Algorithms (PSOs) to be implemented on multi- and many-cores. These benchmarks are named function based benchmarks due to their dependence on the PBAs' functions. Furthermore, the software-hardware mapping with the most performance gain is suggested.

  • Cache locking optimization in java virtual machine

    Cache plays an important role in multilevel storage system. It can greatly reduce the memory access latency. So the cache hit rate has a significant impact on the performance of the application. Many processors provide cache locking mechanism, which can lock the certain lines in cache. It enables an application to affect the cache replacement decisions under software control. This paper presents a novel method, which uses cache locking mechanism to reduce the run-time of java virtual machine (JVM). JVM often uses just-in-time compiler (JIT) to improve the performance. JIT compiles the method that has been invoked certain times, and then JVM executes the compiled method when invoking this method the next time. This paper analyzes the calling situation of the compiled method in JVM, and then proposes a heuristic approach to lock the compiled method in cache for an appropriate period. It can reduce cache miss rate when JVM executes the compiled method. The algorithm has been implemented in HotSpot based on Loongson-3A. Also, it can be implemented in other run-time systems. Experiment results show that the cache locking heuristic algorithm averagely reduces the cache miss rate by 8.5%, and improves the performance by 4% on the benchmark SPECjvm2008.

  • Data fusion in multi sensor platforms for wide-area perception

    There is a strong belief that the improvement of preventive safety applications and the extension of their operative range are achieved by the deployment of multiple sensors with wide fields of view (FOV). The paper contributes to the solution of the problem and introduces distributed sensor data fusion architectures and algorithms for an efficient deployment of multiple sensors that give redundant or complementary information for the moving objects. The proposed fusion architecture is based on a modular approach allowing exchangeability and benchmarking using the output of individual trackers, whereas the fusion algorithm gives a solution to the track management problem and the coverage of wide perception areas. The test case is LATERAL SAFE sensor configuration, which monitors the rear and lateral areas of the vehicle. Results show that with the given approach the system is able to maintain the ID of all objects in transition (an object enters a sensor's FOV) and blind areas (no sensor coverage)

  • Quasi-algebraic decompositions of switching functions

    Brayton (1982-90) and others have developed a rich theory of decomposition of switching functions based on algebraic manipulations of monomials. In this theory, a product g(X/sub g/)/spl middot/h(X/sub h/) is algebraic if X/sub g//spl cap/X/sub h/=O. There are efficient methods for determining if a function has an algebraic product. If a function does not have an algebraic product, then there are good methods for obtaining a decomposition of the form f=g/spl middot/h+r where g/spl middot/h is an algebraic product. Algebraic decompositions have the desirable properties that they are canonical and preserve testability. In this paper we generalize the concept of an algebraic product to decompositions of the form f(X)=g(X/sub g/)??h(X/sub h/) where ?? is any binary Boolean operation and |X/sub g//spl cap/X/sub h/|=k for some k/spl ges/0. We call these decompositions quasi-algebraic decompositions. We begin by showing that we may restrict ourselves to the case where ?? is +(sum),/spl middot/(product) or /spl oplus/ (enclusive-or). We then give necessary and sufficient conditions for a function to have a quasi-algebraic decomposition for a given X/sub g/ and X/sub h/. If a function has such a decomposition we show how to determine the functions g and h in a canonical manner. We also show that these decompositions are fully SSL testable. Finally, using standard benchmark circuits, we show that quasi algebraic decompositions occur often and are useful in reducing circuit size.

  • Improved particle swarm algorithm for portfolio optimization problem

    Particle swarm optimization (PSO) is a recently proposed population-based random search algorithm, which performs well in some optimization problems. In this paper, we proposed an improved PSO algorithm to solve portfolio selection problems. The proposed approach IPSO employs an opposite mutation operator to enhance the performance of the standard PSO. In order to verify the performance of IPSO, we test it on five well-known benchmark function optimization problems. At last, we use IPSO to solve a classical portfolio selection problem. The results show that the proposed approach is effective and achieves better results than standard PSO.

  • A new approach to solving false path problem in timing analysis

    A novel approach to solving the false path problem is proposed. The approach is based on an extended Boolean algebra and is capable of modeling the logic and timing behavior of logic networks in terms of modified Boolean functions. By applying algebraic manipulations, one can use this approach to extract correct timing information such as path delays as well as the input vectors to activate the sensitizable paths. There are two innovative ideas involved in the approach: (1) an algebraic method is used to deal with the problem of delay analysis, and (2) the rising and falling delays of each node are extracted separately. The approach has been implemented and tested on ISCAS benchmarks.<<ETX>>

  • An effective Multi-Objective task scheduling algorithm using Min-Max normalization in cloud computing

    Cloud computing has gained enormous popularity both in business and academia due its on demand service over Internet to the customers on pay-as-you-go model. Task scheduling in cloud computing is a well known problem that has been paid enormous attention. This is even more challenging, particularly for multi-cloud environment. Due to its NP-Hardness, many heuristics have been developed recently. In this paper, we also present a task scheduling algorithm which is based on the popular Min-Max normalization technique in data mining. We refer our proposed algorithm as Normalized Multi-Objective Min-Min Max-Min Scheduling (NMOMXS). Through simulation, the algorithm is shown to outperform two well known existing algorithms in terms of makespan and resource utilization.



Standards related to Benchmark testing

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IEEE Recommended Practice for Determining the Peak Spatial-Average Specific Absorption Rate (SAR) in the Human Head from Wireless Communications Devices: Measurement Techniques

To specify protocols for the measurement of the peak spatial-average specific absorption rate (SAR) in a simplified model of the head of users of hand-held radio transceivers used for personal wireless communications services and intended to be operated while held next to the ear. It applies to contemporary and future devices with the same or similar operational characteristics as contemporary ...



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