Conferences related to Binary decision diagrams

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2020 59th IEEE Conference on Decision and Control (CDC)

The CDC is the premier conference dedicated to the advancement of the theory and practice of systems and control. The CDC annually brings together an international community of researchers and practitioners in the field of automatic control to discuss new research results, perspectives on future developments, and innovative applications relevant to decision making, automatic control, and related areas.


2020 IEEE International Conference on Industrial Engineering and Engineering Management (IEEM)

All topics related to engineering and technology management, including applicable analytical methods and economical/social/human issues to be considered in making engineering decisions.


IGARSS 2020 - 2020 IEEE International Geoscience and Remote Sensing Symposium

All fields of satellite, airborne and ground remote sensing.


2019 Annual Reliability and Maintainability Symposium (RAMS)

Tutorials and original papers on reliability, maintainability, safety, risk management, and logistics


2019 Chinese Control And Decision Conference (CCDC)

Chinese Control and Decision Conference is an annual international conference to create a forum for scientists, engineers and practitioners throughout the world to present the latest advancement in Control, Decision, Automation, Robotics and Emerging Technologies.

  • 2018 Chinese Control And Decision Conference (CCDC)

    Chinese Control and Decision Conference is an annual international conference to create a forum for scientists, engineers and practitioners throughout the world to present the latest advancement in Control, Decision, Automation, Robotics and Emerging Technologies.

  • 2017 29th Chinese Control And Decision Conference (CCDC)

    Chinese Control and Decision Conference is an annual international conference to create a forum for scientists, engineers and practitioners throughout the world to present the latest advancement in Control, Decision, Automation, Robotics and Emerging Technologies.

  • 2016 Chinese Control and Decision Conference (CCDC)

    Chinese Control and Decision Conference is an annual international conference to create aforum for scientists, engineers and practitioners throughout the world to present the latestadvancement in Control, Decision, Automation, Robotics and Emerging Technologies.

  • 2015 27th Chinese Control and Decision Conference (CCDC)

    Chinese Control and Decision Conference is an annual international conference to create a forum for scientists, engineers and practitioners throughout the world to present the latest advancement in Control, Decision, Automation, Robotics and Emerging Technologies.

  • 2014 26th Chinese Control And Decision Conference (CCDC)

    Chinese Control and Decision Conference is an annual international conference to create aforum for scientists, engineers and practitioners throughout the world to present the latestadvancement in Control, Decision, Automation, Robotics and Emerging Technologies.

  • 2013 25th Chinese Control and Decision Conference (CCDC)

    Chinese Control and Decision Conference is an annual international conference to create a forum for scientists, engineers and practitioners throughout the world to present the latest advancement in Control, Decision, Automation, Robotics and Emerging Technologies.

  • 2012 24th Chinese Control and Decision Conference (CCDC)

    Chinese Control and Decision Conference is an annual international conference to create a forum for scientists, engineers and practitioners throughout the world to present the latest advancement in Control, Decision, Automation, Robotics and Emerging Technologies.

  • 2011 23rd Chinese Control and Decision Conference (CCDC)

    Chinese Control and Decision Conference is an annual international conference to create a forum for scientists, engineers and practitioners throughout the world to present the latest advancement in Control, Decision, Automation, Robotics and Emerging Technologies.

  • 2010 Chinese Control and Decision Conference (CCDC)

    Chinese Control and Decision Conference is an annual international conference to create a forum for scientists, engineers and practitioners throughout the world to present the latest advancement in Control, Decision, Automation, Robotics and Emerging Technologies

  • 2009 Chinese Control and Decision Conference (CCDC)

    Chinese Control and Decision Conference is an annual international conference to create a forum for scientists, engineers and practitioners throughout the world to present the latest advancement in Control, Decision, Automation, Robotics and Emerging Technologies.

  • 2008 Chinese Control and Decision Conference (CCDC)


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Periodicals related to Binary decision diagrams

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Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...


Computational Biology and Bioinformatics, IEEE/ACM Transactions on

Specific topics of interest include, but are not limited to, sequence analysis, comparison and alignment methods; motif, gene and signal recognition; molecular evolution; phylogenetics and phylogenomics; determination or prediction of the structure of RNA and Protein in two and three dimensions; DNA twisting and folding; gene expression and gene regulatory networks; deduction of metabolic pathways; micro-array design and analysis; proteomics; ...


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


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Most published Xplore authors for Binary decision diagrams

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Xplore Articles related to Binary decision diagrams

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Circuit based quantification: back to state set manipulation within unbounded model checking

Design, Automation and Test in Europe, 2005

A non-canonical circuit-based state set representation is used to perform quantifier elimination efficiently. The novelty of this approach lies in adapting equivalence checking and logic synthesis techniques to the goal of compacting circuit based state set representations resulting from existential quantification. The method can be efficiently combined with other verification approaches such as inductive and SAT-based pre-image verifications.


A New Assessment Method for System Reliability Based on Dynamic Fault Tree

2010 International Conference on Intelligent Computation Technology and Automation, 2010

According to the deficiency of traditional Markov chain approach in dynamic fault tree analysis, a new modular method for system reliability analysis is proposed. This paper focuses on dividing the fault tree of system into independent subtrees using a linear-time algorithm, and the processing method for different subtrees: Binary decision diagram solution for static subtrees and Bayesian Network solution for ...


Simulation-based design error diagnosis and correction in combinational digital circuits

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), 1999

This paper describes an approach to design error diagnosis and correction in combinational digital circuits. Our approach targets small errors introduced during the design process or due to specification changes. We incrementally use simulation to identify suspect nets, and then attempt correction based on our error model. We use multiple iterations to handle multiple errors. Experimental results on ISCAS'85 benchmarks ...


BDD FTEST: fast, backtrack-free test generator based on binary decision diagram representation

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, 1995

This paper presents a new approach for generating test vectors for combinational circuits. In the approach presented here, the automatic test generator, called BDD FTEST, uses an algebraic method to find a set of test vectors for single stuck lines. For all the circuits analyzed, the algorithm is faster than previously algebraic methods. Experimental results demonstrate that, for most circuits, ...


BDD circuit optimization for path delay fault testability

Euromicro Symposium on Digital System Design, 2004. DSD 2004., 2004

The complexity of integrated circuits is rapidly growing. This leads to more and more time and money spent on the test of these circuits. Besides minimizing the logic needed for a given function the testability of the resulting circuit becomes a major issue during synthesis. One way to synthesize a circuit for a given function is to directly convert the ...


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Educational Resources on Binary decision diagrams

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IEEE.tv Videos

Energy Efficiency of MRR-based BDD Circuits - Ozan Yakar - ICRC San Mateo, 2019
Reducing Binary Quadratic Forms for More Scalable Quantum Annealing - IEEE Rebooting Computing 2017
Computing Based on Material Training: Application to Binary Classification Problems - IEEE Rebooting Computing 2017
An Introduction to Computational Intelligence in Multi-Criteria Decision-Making: The Intersection of Search, Preference Tradeoff
Bayesian Perception & Decision from Theory to Real World Applications
Analog to Digital Types
Fuzzy and Soft Methods for Multi-Criteria Decision Making - Ronald R Yager - WCCI 2016
Algorithmic Decision Making: Impacts and Implications - IEEE Internet Initiative Webinar
Noise-Shaped Active SAR Analog-to-Digital Converter - IEEE Circuits and Systems Society (CAS) Distinguished Lecture
Fusing Simultaneously Acquired EEG and fMRI to Infer Spatiotemporal Dynamics of Cognition in the Human Brain - IEEE Brain Workshop
An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms - Jun Shiomi - ICRC 2018
Probing the Universe with Gravitational Waves - Applied Superconductivity Conference 2018
Coal Gasification at Polk Power Station
David Forney - IEEE Medal of Honor 2016
Social Implications: Perils & Promises of AI - IEEE AI & Ethics Summit 2016
WIE: Our Own Voices - Noel Schulz, Kansas State University
IEEE Authoring Parts 1 and 2: Publishing Choices
Robotics History: Narratives and Networks Oral Histories: Max Mintz
PGX Clinical Decision Support Implementation - Peter Hulick - IEEE EMBS at NIH, 2019
Crisis or Opportunity?: The Economic Impact on Underrepresented Communities - IEEE WIE ILC 2020 Virtual Series

IEEE-USA E-Books

  • Circuit based quantification: back to state set manipulation within unbounded model checking

    A non-canonical circuit-based state set representation is used to perform quantifier elimination efficiently. The novelty of this approach lies in adapting equivalence checking and logic synthesis techniques to the goal of compacting circuit based state set representations resulting from existential quantification. The method can be efficiently combined with other verification approaches such as inductive and SAT-based pre-image verifications.

  • A New Assessment Method for System Reliability Based on Dynamic Fault Tree

    According to the deficiency of traditional Markov chain approach in dynamic fault tree analysis, a new modular method for system reliability analysis is proposed. This paper focuses on dividing the fault tree of system into independent subtrees using a linear-time algorithm, and the processing method for different subtrees: Binary decision diagram solution for static subtrees and Bayesian Network solution for dynamic subtrees, respectively. In addition, an approach is also provided for mapping some dynamic logic gates into discrete-time Bayesian network. At last, the modular method has been applied to assess the reliability of a satellite key device and the results have shown that the proposed method can overcome the state explosion problem, and is useful for assessing the reliability of large and complex systems.

  • Simulation-based design error diagnosis and correction in combinational digital circuits

    This paper describes an approach to design error diagnosis and correction in combinational digital circuits. Our approach targets small errors introduced during the design process or due to specification changes. We incrementally use simulation to identify suspect nets, and then attempt correction based on our error model. We use multiple iterations to handle multiple errors. Experimental results on ISCAS'85 benchmarks are shown for circuits containing up to four random errors. Diagnosis and correction can be done quickly, with the bulk of the time going to diagnosis. Our tool is accurate in that even with multiple errors present, the corrected circuit is identical to the original most of the time.

  • BDD FTEST: fast, backtrack-free test generator based on binary decision diagram representation

    This paper presents a new approach for generating test vectors for combinational circuits. In the approach presented here, the automatic test generator, called BDD FTEST, uses an algebraic method to find a set of test vectors for single stuck lines. For all the circuits analyzed, the algorithm is faster than previously algebraic methods. Experimental results demonstrate that, for most circuits, our algorithm can generate test vectors for all faults in a very short time, particularly for large circuits like the c7552.

  • BDD circuit optimization for path delay fault testability

    The complexity of integrated circuits is rapidly growing. This leads to more and more time and money spent on the test of these circuits. Besides minimizing the logic needed for a given function the testability of the resulting circuit becomes a major issue during synthesis. One way to synthesize a circuit for a given function is to directly convert the binary decision diagram (BDD) of that function into a circuit. It is known that optimizations of the BDD transfer to the derived circuit. Therefore in this paper we evaluate different optimization techniques for BDDs based on variable reordering with respect to the path delay fault testability of the resulting circuit. We show an optimization strategy that allows to compromise during synthesis between logic size and testability.

  • Shared binary decision diagram with attributed edges for efficient Boolean function manipulation

    The efficiency of Boolean function manipulation depends on the form of representation of Boolean functions. Binary decision diagrams (BDDs) are graph representations proposed by S.B. Akers (1978) and R.E. Bryant (1985). BDDs have some properties which can be used to enable efficient Boolean function manipulation. The authors describe a technique of more efficient Boolean function manipulation that uses shared binary decision diagrams (SBDDs) with attributed edges. The implements include an ordering algorithm of input variables and a method of handling 'don't care'. A Boolean function manipulator using the above methods is developed and it is shown that the manipulator is very efficient in terms of speed and storage.<<ETX>>

  • Wireless local loop implementation

    Wireless local loop as a means of connecting subscribers to a telecommunications network is becoming a more popular method in the face of competition and customer demands. This paper addresses some of the new problems and demands which will be faced by a telecommunications operator. The expected implementation of wireless local loop technologies in an existing network will raise new problems, not faced by the operator before. In this respect Telkom SA is no exception. In Telkom the second-generation cordless telephone (CT2) is the first of these new technologies.

  • A Fully Implicit Algorithm for Exact State Minimization

    State minimization of incompletely specified machines is an important step of FSM synthesis. An exact algorithm consists of generation of prime compatibles and solution of a binate covering problem. This paper presents an implicit algorithm for exact state minimization of FSM's. We describe how to do implicit prime computation and implicit binate covering. We show that we can handle sets of compatibles and prime compatibles of cardinality up to 2/sup 1500/. We present the first published algorithm for fully implicit exact binate covering. We show that we can reduce and solve binate tables with up to 10 /sup 6/ rows and columns. The entire branch-and-bound procedure is carried on implicitly. We indicate also where such examples arise in practice.

  • Sibling-substitution-based BDD minimization using don't cares

    In many computer-aided design tools, binary decision diagrams (BDDs) are used to represent Boolean functions. To increase the efficiency and capability of these tools, many algorithms have been developed to reduce the size of the BDDs. This paper presents heuristic algorithms to minimize the size of the BDDs representing incompletely specified functions by intelligently assigning don't cares to binary values. Experimental results show that new algorithms yield significantly smaller BDDs compared with existing algorithms yet still require manageable run-times. These algorithms are particularly useful for synthesis application where the structure of the hardware/software is derived from the BDD representation of the function to implement because the minimization quality is more critical than the minimization speed in these applications.

  • Formal verification of self-testing properties of combinational circuits

    This paper proposes a method of formal verification of self-testing (ST) property of combinational circuits using logic function manipulation. In this method we show that the problem of verification of ST property can be transformed to satisfiability problem of a decision function formed from characteristic functions of the circuit's output code words. Then the problem can be resolved using binary decision diagrams (BDD) efficiently. Experimental results show the effectiveness of the proposed method.



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