Conferences related to Binary search trees

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2021 IEEE International Conference on Fuzzy Systems (FUZZ-IEEE)

FUZZ-IEEE 2021 will represent a unique meeting point for scientists and engineers, both from academia and industry, to interact and discuss the latest enhancements and innovations in the field. The topics of the conference will cover all the aspects of theory and applications of fuzzy sets, fuzzy logic and associated approaches (e.g. aggregation operators such as the Fuzzy Integral), as well as their hybridizations with other artificial and computational intelligence techniques.


2020 IEEE International Symposium on Antennas and Propagation and North American Radio Science Meeting

The joint meeting is intended to provide an international forum for the exchange of information on state of the art research in the area of antennas and propagation, electromagnetic engineering and radio science


2020 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

CVPR is the premier annual computer vision event comprising the main conference and several co-located workshops and short courses. With its high quality and low cost, it provides an exceptional value for students, academics and industry researchers.

  • 2019 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premier annual computer vision event comprising the main conference and severalco-located workshops and short courses. With its high quality and low cost, it provides anexceptional value for students, academics and industry researchers.

  • 2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premier annual computer vision event comprising the main conference and several co-located workshops and short courses. With its high quality and low cost, it provides an exceptional value for students, academics and industry researchers.

  • 2017 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premiere annual Computer Vision event comprising the main CVPR conferenceand 27co-located workshops and short courses. With its high quality and low cost, it provides anexceptional value for students,academics and industry.

  • 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premiere annual Computer Vision event comprising the main CVPR conference and 27 co-located workshops and short courses. With its high quality and low cost, it provides an exceptional value for students, academics and industry.

  • 2015 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    computer, vision, pattern, cvpr, machine, learning

  • 2014 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premiere annual Computer Vision event comprising the main CVPR conference and 27 co-located workshops and short courses. Main conference plus 50 workshop only attendees and approximately 50 exhibitors and volunteers.

  • 2013 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    CVPR is the premiere annual Computer Vision event comprising the main CVPR conference and 27 co-located workshops and short courses. With its high quality and low cost, it provides an exceptional value for students, academics and industry.

  • 2012 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    Topics of interest include all aspects of computer vision and pattern recognition including motion and tracking,stereo, object recognition, object detection, color detection plus many more

  • 2011 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    Sensors Early and Biologically-Biologically-inspired Vision, Color and Texture, Segmentation and Grouping, Computational Photography and Video

  • 2010 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    Concerned with all aspects of computer vision and pattern recognition. Issues of interest include pattern, analysis, image, and video libraries, vision and graphics, motion analysis and physics-based vision.

  • 2009 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

    Concerned with all aspects of computer vision and pattern recognition. Issues of interest include pattern, analysis, image, and video libraries, vision and graphics,motion analysis and physics-based vision.

  • 2008 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

  • 2007 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

  • 2006 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

  • 2005 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)


2020 IEEE International Conference on Image Processing (ICIP)

The International Conference on Image Processing (ICIP), sponsored by the IEEE SignalProcessing Society, is the premier forum for the presentation of technological advances andresearch results in the fields of theoretical, experimental, and applied image and videoprocessing. ICIP 2020, the 27th in the series that has been held annually since 1994, bringstogether leading engineers and scientists in image and video processing from around the world.


2020 IEEE International Conference on Plasma Science (ICOPS)

IEEE International Conference on Plasma Science (ICOPS) is an annual conference coordinated by the Plasma Science and Application Committee (PSAC) of the IEEE Nuclear & Plasma Sciences Society.


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Periodicals related to Binary search trees

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Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Automatic Control, IEEE Transactions on

The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...


Automation Science and Engineering, IEEE Transactions on

The IEEE Transactions on Automation Sciences and Engineering (T-ASE) publishes fundamental papers on Automation, emphasizing scientific results that advance efficiency, quality, productivity, and reliability. T-ASE encourages interdisciplinary approaches from computer science, control systems, electrical engineering, mathematics, mechanical engineering, operations research, and other fields. We welcome results relevant to industries such as agriculture, biotechnology, healthcare, home automation, maintenance, manufacturing, pharmaceuticals, retail, ...


Biomedical Engineering, IEEE Transactions on

Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.


Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


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Most published Xplore authors for Binary search trees

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Xplore Articles related to Binary search trees

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Video Ghost Cancelling: Evaluation By Computer Simulations And Laboratory Tests

IEEE 1992 International Conference on Consumer Electronics Digest of Technical Papers, 1992

None


A 4-level storage 4 Gb DRAM

1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers, 1997

Bit-cost reduction is one of the most serious issues for file application DRAMs. Chip size reduction or density increase has been an effective solution. Lithographic technology has permitted this density increase through 70% reduction in the minimum design rule for each subsequent DRAM generation. However, for further density increase, another memory cell reduction technology is needed. Multi-level storage is one ...


A DRAM technology using MIM BST capacitor for 0.15 /spl mu/m DRAM generation and beyond

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325), 1999

Recently, 1 Gb DRAM based on the 0.18 /spl mu/m technology node (generation) and 0.15 /spl mu/m technology node for 4 Gb DRAM have been successfully demonstrated. These two technology generations are based on MIS capacitors using Ta/sub 2/O/sub 5/ dielectric. The extension of Ta/sub 2/O/sub 5/ MIS capacitors below 0.15 /spl mu/m technology is considered to be difficult due ...


Tunable multiband power amplifier using thin-film BST varactors for 4G handheld applications

2010 IEEE Radio and Wireless Symposium (RWS), 2010

A new methodology for multiband tunable power amplifiers (PA) using barium- strontium-titanate (BST) varactors is presented. A prototype tunable power amplifier has been developed and its performance is evaluated in context of the upcoming 4G scenario which demands for multimode/ multiband power amplifiers capable of operating over multiple frequency bands. The tunable PA requires two tuning voltages at the output ...


High performance 60 nm CMOS technology enhanced with BST (body-slightly-tied) structure SOI and Cu/low-k (k=2.9) interconnect for microprocessors

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303), 2002

We have developed high performance/low active power CMOS technology for microprocessor products. This features (1) drive current enhancement with high-dose low-energy ion implantation (I/I) for S/D extension, (2) body- slightly-tied (BST) CMOS/SOI with partial trench isolation and local channel doping, (3) Cu interconnect with low-k (k=2.9) dielectric.


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Educational Resources on Binary search trees

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IEEE.tv Videos

2015 IEEE Honors: IEEE Jack S. Kilby Signal Processing Medal - Harry L. Van Trees
Reducing Binary Quadratic Forms for More Scalable Quantum Annealing - IEEE Rebooting Computing 2017
Computing Based on Material Training: Application to Binary Classification Problems - IEEE Rebooting Computing 2017
Search Techniques
Learning from Katrina: Search and Rescue Robots for Natural Disasters
Energy Efficiency of MRR-based BDD Circuits - Ozan Yakar - ICRC San Mateo, 2019
Noise-Shaped Active SAR Analog-to-Digital Converter - IEEE Circuits and Systems Society (CAS) Distinguished Lecture
Probing the Universe with Gravitational Waves - Applied Superconductivity Conference 2018
New Immersive Mediums - The Search For Egg Yolk: IEEE VICS 2018
An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms - Jun Shiomi - ICRC 2018
LDA to Find User Archetypes for Search & Matching
"What is Big Data Analytics and Why Should I Care?" - Big Data Analytics Tutorial Part 1
Computer-Assisted Audiovisual Language Learning
An Introduction to Computational Intelligence in Multi-Criteria Decision-Making: The Intersection of Search, Preference Tradeoff
Some Recent Work in Computational Intelligence for Software Engineering
Bari-Bari-II: Jack-Up Rescue Robot with Debris Opening Function
IEEE Xplore: Insider Tips to Improve Your Productivity - Part 1
MyComputer: You Choose, We Deliver
IEEE Xplore: Insider Tips to Improve Your Productivity - Part 4
Dynamic Selection of Evolutionary Algorithm Operators Based on Online Learning and Fitness Landscape Metrics

IEEE-USA E-Books

  • Video Ghost Cancelling: Evaluation By Computer Simulations And Laboratory Tests

    None

  • A 4-level storage 4 Gb DRAM

    Bit-cost reduction is one of the most serious issues for file application DRAMs. Chip size reduction or density increase has been an effective solution. Lithographic technology has permitted this density increase through 70% reduction in the minimum design rule for each subsequent DRAM generation. However, for further density increase, another memory cell reduction technology is needed. Multi-level storage is one circuit technology that can reduce the effective cell size since it allows the storage of multiple voltage levels in a single memory cell functioning as a multi-bit memory. When four levels are stored in a single memory cell, the effective cell size is halved. The authors show that a charge-coupling sense amplifier, charge-sharing restore, and time-shared sensing increase speed and reduce sense-circuit area for 4 Gb DRAM.

  • A DRAM technology using MIM BST capacitor for 0.15 /spl mu/m DRAM generation and beyond

    Recently, 1 Gb DRAM based on the 0.18 /spl mu/m technology node (generation) and 0.15 /spl mu/m technology node for 4 Gb DRAM have been successfully demonstrated. These two technology generations are based on MIS capacitors using Ta/sub 2/O/sub 5/ dielectric. The extension of Ta/sub 2/O/sub 5/ MIS capacitors below 0.15 /spl mu/m technology is considered to be difficult due to insufficient cell capacitance. It is widely accepted that the MIM capacitor using high dielectric constant material is inevitable for 0.15 /spl mu/m technology and beyond. Although many studies to use high dielectric material have been reported, those studies are not adequate for 0.15 /spl mu/m technology and beyond because most of the studies are either based on a simple capacitor module process or based on large feature size design rules. In this paper, for the first time, a DRAM technology using BaSrTiO/sub 3/ (BST) MIM capacitors is developed with 0.15 /spl mu/m technology.

  • Tunable multiband power amplifier using thin-film BST varactors for 4G handheld applications

    A new methodology for multiband tunable power amplifiers (PA) using barium- strontium-titanate (BST) varactors is presented. A prototype tunable power amplifier has been developed and its performance is evaluated in context of the upcoming 4G scenario which demands for multimode/ multiband power amplifiers capable of operating over multiple frequency bands. The tunable PA requires two tuning voltages at the output matching network as well as an additional tuning voltage for a novel tunable 2<sup>nd</sup> harmonic termination. The PA is continuously tunable from 1700 to 2300 MHz, covering multiple bands. Tunable PA measurements with LTE signals show a maximum gain of 27 dB with Pmax of 24.1 dBm and an EVM of 6% using BST varactors having Q-factors not more then 30 at sub-2 GHz frequencies.

  • High performance 60 nm CMOS technology enhanced with BST (body-slightly-tied) structure SOI and Cu/low-k (k=2.9) interconnect for microprocessors

    We have developed high performance/low active power CMOS technology for microprocessor products. This features (1) drive current enhancement with high-dose low-energy ion implantation (I/I) for S/D extension, (2) body- slightly-tied (BST) CMOS/SOI with partial trench isolation and local channel doping, (3) Cu interconnect with low-k (k=2.9) dielectric.

  • An Enhanced Anti-collision Algorithm in RFID Based on Counter and Stack

    Radio frequency identification has been developed for many years and it got much attention from researchers recently as there are lots of applications being used practically in the real world. Owing to the shared wireless channel between tags and reader during communication, the tag collision arbitration is a significant issue for reducing the communication overhead. This paper presents a novel anti-collision algorithm named as EAA (enhanced anti- collision algorithm) which is based on ABS (Adaptive Binary Splitting) algorithm proposed by Myung et al. We improve the ABS algorithm, and inherit the advantages of the ABS algorithm. EAA uses counter, stack, and Manchester code (Bo Chen et al., 2005) to reduce the probability of collision efficiently. Compared to the methods proposed by other researchers (Bo Feng, 2006), (Jihoon Myung, 2006) the performance evaluation shows that the proposed scheme in this paper uses fewer timeslots for indentifying tags.

  • The cleaning at a back surface and edge of a wafer for introducing Cu metalization process

    Cu metalization has been introduced in high-speed CMOS LSIs in order to achieve low electrical resistivity. This means Cu contamination can be spread all over semiconductor equipment by the wafers. To protect the other wafers without Cu from Cu cross-contamination, we have demonstrated a method that can clean the back surface and selectively clean the edge of a wafer simultaneously without any masks. This method performs the cleaning by optimizing the overhang of chemicals in the single-wafer system. We have also demonstrated a new edge extractor that can be used to perform the quantitative evaluation of Cu contamination at the wafer edge. The combination of the edge cleaning and the edge evaluation is useful for introducing not only Cu but also new exotic materials such as Ta/sub 2/O/sub 5/ and BST.

  • Effect of rare earth elements doping on the electrical properties of (Ba,Sr)TiO<inf>3</inf> thin film capacitors

    Barium strontium titanate (BST) thin film capacitors are being intensively investigated for tunable microwave devices, because of their high permittivity, low dielectric loss in the microwave region and field dependent permittivity. This study investigates the effect of rare earth elements doping on the electrical properties of BST thin film capacitors. BST thin films were deposited by an RF magnetron sputtering technique on Si wafers. BST films were prepared with Y concentrations of 0-5%. Lattice parameters were measured using synchrotron radiation X-ray analysis. The results show that Y doped BST thin film capacitors exhibit not only significantly higher permittivity but also low leakage current density as compared to nominally undoped capacitors. X-ray diffraction results show the film strain state strongly depends on film composition with tunability decreasing with increasing tensile strain.

  • An effective approach for achieving fault tolerance in hypercubes

    The hypercube network is an attractive structure for parallel processing because of its regularity. The problem of tolerating faulty processors in hypercubes has been studied by many researchers, either by using spares or by reconfiguration. In this paper, we present algorithms for achieving fault tolerance in hypercubes using spanning trees, without requiring additional spare nodes. We present two algorithms; one uses completely unbalanced spanning trees (CUST) and the other uses balanced spanning trees (BST). Both algorithms use, at most, one used link and one unused link for every reconstructed path in the reconfigured hypercube. The algorithms are optimal, in terms of the reconfiguration time and may increase the congestion of a link by, at most, one with no extra-dilation. Single-fault coverage of 100% and almost 100% fault coverage of double and triple faults are achieved by the proposed algorithms for hypercubes having a dimension of n/spl ges/10.

  • Coating of planar Barium-Strontium-Titanate thick-film varactors to increase tunability

    Scaled varactors on a Barium-Strontium-Titanate (BST) thick-film are produced and characterized. The tunability of the scaled varactors is measured at up to 12.5 V/mum effective tuning field-strength in the planar varactors' air gap. To increase the effective tuning field-strength without breakdown and therefore to increase the tunability of the varactor the planar structure is covered with Parylene. As a result of the Parylene coating, a tuning field- strength of up to 29 V/mum can be applied to the varactors' gap which results in a capacitance tuning of 44.5 %. The humidity dependency of the quality factor of BST components based on porous thick-film can be eliminated. By sealing the porous surface, the quality factor of the varactors is significantly increased.



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