Conferences related to CMOS memory circuits

Back to Top

2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2020 IEEE International Magnetic Conference (INTERMAG)

INTERMAG is the premier conference on all aspects of applied magnetism and provides a range of oral and poster presentations, invited talks and symposia, a tutorial session, and exhibits reviewing the latest developments in magnetism.


2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


More Conferences

Periodicals related to CMOS memory circuits

Back to Top

Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


More Periodicals

Most published Xplore authors for CMOS memory circuits

Back to Top

Xplore Articles related to CMOS memory circuits

Back to Top

A 1Mb ROM with on chip ECC for yield enhancement

1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1983

None


BiCMOS circuitry: the best of both worlds

IEEE Spectrum, 1989

The growing use of BiCMOS circuits, which benefit from the combination of low CMOS power consumption and high bipolar speed, is examined. The tradeoffs that BiCMOS circuits entail and the drawbacks that have hindered their wide adoption, especially for digital applications, are discussed. The growing opportunity for BiCMOS, as CMOS ICs have become more complicated and the benefits of scaling ...


Fully static 16Kb bulk CMOS RAM

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1980

A coplanar Si-gate CMOS process used in the design of a fully static 16Kb bulk CMOS RAM with a six-transistor cell will be covered. RAM offers a typical 95ns access time with 200mW power dissipation and 1μW standby power.


A 40ns CMOS E2PROM

1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1982

This Paper will report on an 8K CMOS/SOS E2PROM with an access time of 38ns at 5V, 60mW power dissipation and write voltage as low as 12V.


A full-custom self-timed DSP processor implementation

Proceedings of the 23rd European Solid-State Circuits Conference, 1997

Asynchronous self-timed control and DCVSL logic have been used in the construction of a complete VLSI processor, targeted for DSP algorithms. The 16-bit architecture includes both data and program memory, and uses a data- stationary control structure. The experimental VLSI circuit includes 143 000 transistors and has been fabricated using 0.8µm CMOS.


More Xplore Articles

Educational Resources on CMOS memory circuits

Back to Top

IEEE.tv Videos

Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
Erasing Logic-Memory Boundaries in Superconductor Electronics - Vasili Semenov: 2016 International Conference on Rebooting Computing
IMS 2011 Microapps - Memory Effects in RF Circuits: Definition, Manifestations and Fast, Accurate Simulation
Superconductive Energy-Efficient Computing - ASC-2014 Plenary-series - 6 of 13 - Wednesday 2014/8/13
IRDS: Beyond CMOS & Emerging Research Materials - Shamik Das at INC 2019
R. Jacob Baker - SSCS Chip Chat Podcast, Episode 4
A 39GHz 64-Element Phased-Array CMOS Transceiver - Yun Wang - RFIC 2019 Showcase
A High Efficiency 39GHz CMOS Cascode Amplifier for 5G Applications - H.C. Park - RFIC 2019 Showcase
R. Jacob Baker: CMOS & DRAM Circuit Design
Rajiv V. Joshi - 2018 Daniel E. Noble Award for Emerging Technologies at IEEE ISSCC
X-band NMOS & CMOS Cross-Coupled DCO’s with “Folded” Common Mode Resonators - Run Levinger - RFIC 2019 Showcase
Devices: Next 20 Years Panel - Mustafa Badaroglu at INC 2019
New Paradigm for Fault-Tolerant Computing with Interconnect Crosstalks - Naveen Kumar Macha - ICRC 2018
Accelerating Machine Learning with Non-Volatile Memory: Exploring device and circuit tradeoffs - Pritish Narayanan: 2016 International Conference on Rebooting Computing
The Josephson Effect: Josephson Digital Electronics in the Soviet Union
Raspberry Pi High Speed SerDes Characterization Platform
Brooklyn 5G Summit: Going the Distance with CMOs: mm-Waves and Beyond
"Reversible/Adiabatic Classical Computation An Overview" (Rebooting Computing)
Reconfigurable 60-GHz Radar Transmitter SoC - Wooram Lee - RFIC 2019 Showcase
ON-CHIP VOLTAGE AND TIMING DIAGNOSTIC CIRCUITS

IEEE-USA E-Books

  • A 1Mb ROM with on chip ECC for yield enhancement

    None

  • BiCMOS circuitry: the best of both worlds

    The growing use of BiCMOS circuits, which benefit from the combination of low CMOS power consumption and high bipolar speed, is examined. The tradeoffs that BiCMOS circuits entail and the drawbacks that have hindered their wide adoption, especially for digital applications, are discussed. The growing opportunity for BiCMOS, as CMOS ICs have become more complicated and the benefits of scaling them less pronounced and harder to realize, is noted. The three basic reasons for using BiCMOS, namely, analog compatibility, increased performance, and reduced system costs, are discussed.<<ETX>>

  • Fully static 16Kb bulk CMOS RAM

    A coplanar Si-gate CMOS process used in the design of a fully static 16Kb bulk CMOS RAM with a six-transistor cell will be covered. RAM offers a typical 95ns access time with 200mW power dissipation and 1μW standby power.

  • A 40ns CMOS E2PROM

    This Paper will report on an 8K CMOS/SOS E2PROM with an access time of 38ns at 5V, 60mW power dissipation and write voltage as low as 12V.

  • A full-custom self-timed DSP processor implementation

    Asynchronous self-timed control and DCVSL logic have been used in the construction of a complete VLSI processor, targeted for DSP algorithms. The 16-bit architecture includes both data and program memory, and uses a data- stationary control structure. The experimental VLSI circuit includes 143 000 transistors and has been fabricated using 0.8µm CMOS.

  • Applications of new technology in power substations

    The authors describe the applications of some of the more modern technologies to instrument designed specifically to operate in utility substation environments. Particular emphasis is placed on the use of CMOS logic, processor, and memory circuits, high-density flexible magnetic disk media, and high-capacity Winchester technology storage devices. The operating history of a number of units over a five-year period is reported, as well as the steps taken to protect these devices in a hostile environment. In addition, areas requiring specific improvement and adaptation are noted.<<ETX>>

  • 0.8 V CMOS content-addressable-memory (CAM) cell circuit with a fast tag-compare capability using bulk PMOS dynamic-threshold (BP-DTMOS) technique based on standard CMOS technology for low-voltage VLSI systems

    This paper reports a novel 0.8 V content addressable memory (CAM) cell circuit with a fast tag-compare capability using the bulk PMOS dynamic-threshold (BP- DTMOS) technique based on standard CMOS technology following the SOI DTMOS technology for low-voltage VLSI systems. Using four PMOS devices with their body controlled dynamically in the tag-compare portion, this CAM cell, which is built in standard bulk CMOS technology using the BP-DTMOS technique, has a faster tag-compare operation at a supply voltage of 0.8 V as compared to the one not using the BP-DTMOS technique.

  • Ferroelectric-based functional pass-gate for low-power VLSI

    A ferroelectric-based functional pass-gate is proposed for low-power logic-in- memory VLSI which makes communication bottlenecks free. Since non-destructive storage and switching functions are merged into a ferroelectric capacitor, active-device counts become small, which reduces the dynamic power dissipation. The use of ferroelectric-based non-volatile storage makes leakage currents cut off. Applying the ferroelectric-based circuitry to binary CAM implementation results in about half dynamic power reduction and 1/22000 static power reduction, compared to a. CMOS implementation under 0.6 /spl mu/m ferroelectric/CMOS.

  • Subthreshold analog performance of channel engineered SOI CMOS devices and circuits for ultra-low power analog/mixed-signal applications

    Subthreshold analog operation of CMOS devices are very attractive in terms of both very low power dissipation and high voltage gain. In this paper, a systematic investigation, with the help of extensive process and device simulations, of the effects of halo doping [both double-halo (DH) and single- halo (SH) or lateral asymmetric channel (LAC)] on the subthreshold analog performance of 100 nm SOI CMOS devices and circuits is reported. CMOS amplifiers made with the halo implanted devices are found to have higher voltage gain over their conventional counterpart.

  • Time memory cell VLSI for the PHENIX drift chamber

    A high-precision Time-to-Digital-Converter VLSI, TMC-PHX1, was developed for the PHENIX drift chamber. The chip contains 4 channels of TDC with two stages of data buffering and a trigger buffering which are necessary for very high rate experiments. In addition to the fixed data size readout, the chip also supports zero-suppression mode readout. The chip records both rising and falling edge timings, and has a least timing count of 0.83 ns/bit and 1.66 ns/bit respectively. A level 1 buffer has a recording depth of 6.8 /spl mu/sec and a readout FIFO has a depth of 128 words. High precision timing was derived from an asymmetric ring oscillator stabilized with a PLL. The chip runs at 4 times faster clock (37.6 MHz) of the RHIC bunch clock, and was fabricated with 0.5 /spl mu/m CMOS gate-array technology.



Standards related to CMOS memory circuits

Back to Top

No standards are currently tagged "CMOS memory circuits"


Jobs related to CMOS memory circuits

Back to Top