CMOSFET circuits

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68 resources related to CMOSFET circuits

Conferences related to CMOSFET circuits

2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.

2020 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges

2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.

2020 IEEE/MTT-S International Microwave Symposium (IMS)

The IEEE International Microwave Symposium (IMS) is the world s foremost conference covering the UHF, RF, wireless, microwave, millimeter-wave, terahertz, and optical frequencies; encompassing everything from basic technologies to components to systems including the latest RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation and more. The IMS includes technical and interactive sessions, exhibits, student competitions, panels, workshops, tutorials, and networking events.

2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)

This is a set of five conferences with a focus on wireless components, applications and systems that affect both now and our future lifestyle. The main niche of these conferences is to bring together technologists, circuit designers, system designers and entrepreneurs at a single event. It was and is the place where these worlds meet, where new processes and systems can be benchmarked against the needs of circuit designers at the bleeding edge of RF systems. This is also an area where today's design compromises can trigger tomorrow's advanced technologies, where dreams can become a reality.

Periodicals related to CMOSFET circuits

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.

All aspects of optical guided-wave science, technology, and engineering in the areas of fiber and cable technologies; active and passive guided-wave componentry (light sources, detectors, repeaters, switches, fiber sensors, etc.); integrated optics and optoelectronics; systems and subsystems; new applications; and unique field trials.

Xplore Articles related to CMOSFET circuits

IEEE International Electron Devices Meeting 2003, 2003

This work describes a new DRAM cell technology, W/WNx/P/sup +/-gate NMOS memory cell (MC) transistors, which has been integrated into a dual-gate CMOS process. Operation speed, data retention time (t/sub REF/), and reliability of high speed DRAMs are dramatically improved by the P/sup +/-gate NMOS cell, having a low-resistance polymetal word line (WL). Transistor performance in the periphery circuit is ...

International Electron Devices Meeting. IEDM Technical Digest, 1997

We present a detailed study of electrical characteristics of sub-3 nm gate oxides grown on nitrogen implanted Si substrates (N/sub 2/ I/I oxides). The new results that advance the understanding of N/sub 2/ I/I oxides are the following: lower tunneling current, higher TDDB lifetime and reduced defect density are reported in N/sub 2/ I/I oxides for the first time. In ...

IEEE Transactions on Semiconductor Manufacturing, 2012

In this paper, a novel bipolar junction transistor (BJT) structure is proposed for high matching characteristics and its performance is compared with a conventional BJT structure. Although the proposed BJT matching structure indicates a decrease of collector current density $J_{C}$ and current gain $\beta$ of about 5.36% and 1.02% compared with those of the conventional BJT structure, the matching characteristics ...

International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), 1999

We have demonstrated three key integration technologies of thermally stable dual-gate CMOSFETs for DRAM-embedded ASICs. These technologies include: (1) a thermally stable W-polycide gate for every MOSFET and CoSi/sub 2/ diffusion for logic CMOS to maintain low resistance, (2) nitrogen implantation into WSi/sub 2/ to prevent lateral dopant diffusion without gate depletion, and (3) a Si/sub 3/N/sub 4//TEOS-BPSG stacked interlayer ...

Proceedings of International Conference on Microelectronic Test Structures, 1996

Experimental results on asymmetry and mismatch (A&M) characteristics are discussed for 0.5 /spl mu/m surface-channel n-MOSFETs and buried-channel p-MOSFETs fabricated by four ion-implantation methods and designed by a conventional and a side-by-side layout. The side-by-side layout is useful to improve A&M caused by source/drain asymmetry. There is not a single choice that simultaneously satisfies the minimum average and deviation values ...

Educational Resources on CMOSFET circuits

IEEE-USA E-Books

• This work describes a new DRAM cell technology, W/WNx/P/sup +/-gate NMOS memory cell (MC) transistors, which has been integrated into a dual-gate CMOS process. Operation speed, data retention time (t/sub REF/), and reliability of high speed DRAMs are dramatically improved by the P/sup +/-gate NMOS cell, having a low-resistance polymetal word line (WL). Transistor performance in the periphery circuit is enhanced by dual-gate CMOSFETs formed with a low temperature process. These technologies offer excellent scalability and fully operating DDR-II SDRAM test chips have been obtained.

• We present a detailed study of electrical characteristics of sub-3 nm gate oxides grown on nitrogen implanted Si substrates (N/sub 2/ I/I oxides). The new results that advance the understanding of N/sub 2/ I/I oxides are the following: lower tunneling current, higher TDDB lifetime and reduced defect density are reported in N/sub 2/ I/I oxides for the first time. In addition, excellent device and circuit performance are demonstrated for dual-gate CMOSFETs with N/sub 2/ VI oxides down to channel lengths under 0.10 /spl mu/m.

• In this paper, a novel bipolar junction transistor (BJT) structure is proposed for high matching characteristics and its performance is compared with a conventional BJT structure. Although the proposed BJT matching structure indicates a decrease of collector current density $J_{C}$ and current gain $\beta$ of about 5.36% and 1.02% compared with those of the conventional BJT structure, the matching characteristics of the collector current $(A_{\rm IC})$ and the current gain $(A_{\beta})$ for the proposed structure are improved by about 31% and 24%. The improved matching characteristic of the proposed structure is believed to be due to the reduced effect of the deep n-well or the reduced current path from emitter to collector.

• We have demonstrated three key integration technologies of thermally stable dual-gate CMOSFETs for DRAM-embedded ASICs. These technologies include: (1) a thermally stable W-polycide gate for every MOSFET and CoSi/sub 2/ diffusion for logic CMOS to maintain low resistance, (2) nitrogen implantation into WSi/sub 2/ to prevent lateral dopant diffusion without gate depletion, and (3) a Si/sub 3/N/sub 4//TEOS-BPSG stacked interlayer for self-aligned contacts (SAC) without boron penetration in PMOSFETs. High-performance CMOSFETs using these technologies and 5 metal layers result in a flexible circuit design which can achieve 6.8 ns access speed in a 64 Mb DRAM-embedded macro with a 0.25 /spl mu/m design rule.

• Experimental results on asymmetry and mismatch (A&M) characteristics are discussed for 0.5 /spl mu/m surface-channel n-MOSFETs and buried-channel p-MOSFETs fabricated by four ion-implantation methods and designed by a conventional and a side-by-side layout. The side-by-side layout is useful to improve A&M caused by source/drain asymmetry. There is not a single choice that simultaneously satisfies the minimum average and deviation values of A&M for all electrical parameters. For minimizing A&M in (I/sub D/ and /spl beta/), (V/sub T/ and S) and I/sub B/, n- and p-MOSFETs fabricated by 7/spl deg//spl times/4-implantation, n-MOSFETs with 0/spl deg/- and 7/spl deg//spl times/4-implantation, and n- and p-MOSFETs with 0/spl deg/- and 7/spl deg//spl times/4-implantation are recommended, respectively. However 0/spl deg/-implanted MOSFETs must not be used because of their inferior punchthrough characteristics.