Conferences related to CMOSFET logic devices

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2020 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2019 IEEE 9th International Nanoelectronics Conferences (INEC)

Topics of Interests (but not limited to)• Application of nanoelectronic• Low-dimensional materials• Microfluidics/Nanofluidics• Nanomagnetic materials• Carbon materials• Nanomaterials• Nanophotonics• MEMS/NEMS• Nanoelectronic• Nanomedicine• Nano Robotics• Spintronic devices• Sensor and actuators• Quality and Reliability of Nanotechnology


2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)

This is a set of five conferences with a focus on wireless components, applications and systems that affect both now and our future lifestyle. The main niche of these conferences is to bring together technologists, circuit designers, system designers and entrepreneurs at a single event. It was and is the place where these worlds meet, where new processes and systems can be benchmarked against the needs of circuit designers at the bleeding edge of RF systems. This is also an area where today's design compromises can trigger tomorrow's advanced technologies, where dreams can become a reality.



Periodicals related to CMOSFET logic devices

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Communications Magazine, IEEE

IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.



Most published Xplore authors for CMOSFET logic devices

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Xplore Articles related to CMOSFET logic devices

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Novel SOI wafer engineering using low stress and high mobility CMOSFET with <100>-channel for embedded RF/analog applications

Digest. International Electron Devices Meeting,, 2002

For high performance RF/analog and logic device technology, novel SOI wafer engineering featuring <100>-channel SOI CMOSFET with high-resistivity substrate is proposed. Mobility of PMOSFET is improved about 16% by changing a channel direction from <110> to <100>. Moreover, the reduction of the drive current in narrow channel PMOSFET is suppressed. The maximum oscillation frequency (f/sub max/) for NMOSFET is improved ...


A BIST circuit for I/sub DDQ/ tests

2003 Test Symposium, 2003

In this paper, an I/sub DDQ/ test time reduction method is proposed which is suitable for BIST approaches. Also, a BIST circuit for I/sub DDQ/ tests, based on the method, is proposed. The layout of a CMOS logic circuit having the BIST circuit is designed and the performance is evaluated by SPICE simulation. The results show us that I/sub DDQ/ ...


Transmission gate-interfaced APDL design

Electronics Letters, 1996

Based on the recent adiabatic pseudo domino logic (APDL), a new circuit structure, transmission gate-interfaced APDL (T-APDL), is proposed to improve the performance of the APDL circuit, especially for power consumption, operating voltage and frequency characteristics. Although an additional transistor is required in the basic T-APDL structure, the power saving compared to APDL is significant and the proposed circuits have ...


EMC issues relating to the design of communicating appliances

1995 Sixth International Conference on Radio Receivers and Associated Systems, 1995

There has been a rapid growth in the use of mobile communications with the emergence of digital radio technologies. In parallel with this PDAs (Personal Digital Assistants) are now starting to enter the market place. The development of commercial products combining both digital electronics and RF (radio frequency) circuits gives rise to some important EMC (electromagnetic compatibility) challenges. These can ...


Design of CMOS self-checking sequential circuits with improved detectability of bridging faults

Electronics Letters, 1994

Problems due to the presence of resistive bridging faults within sequential functional blocks of self-checking circuits are studied, and design criteria aimed at reducing their effects are proposed.<<ETX>>



Educational Resources on CMOSFET logic devices

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IEEE.tv Videos

FinSAL: A Novel FinFET Based Secure Adiabatic Logic for Energy-Efficient and DPA Resistant IoT Devices - Himanshu Thapliyal: 2016 International Conference on Rebooting Computing
IRDS: Beyond CMOS & Emerging Research Materials - Shamik Das at INC 2019
Pt. 2: More Moore: Scaling of CMOS - An Chen - Industry Panel 2, IEEE Globecom, 2019
IRDS: Lithography - Mark Neisser at INC 2019
The Josephson Effect: Josephson Digital Electronics in the Soviet Union
Pt. 2: Beyond CMOS & More-than-Moore - Shamik Das - Industry Panel 2, IEEE Globecom, 2019
IEEE Magnetics Distinguished Lecture - Mitsuteru Inoue
Dynamic Logic Example
Devices: Next 20 Years Panel - Mustafa Badaroglu at INC 2019
A perspective shift from Fuzzy logic to Neutrosophic Logic - Swati Aggarwal
Similarity and Fuzzy Logic in Cluster Analysis
35 Years of Magnetic Heterostructures
BSIM Spice Model Enables FinFET and UTB IC Design
Navigation and Control of Unmanned Vehicles: A Fuzzy Logic Perspective
Perpendicular magnetic anisotropy: From ultralow power spintronics to cancer therapy
Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
The Hertzsprung-Russell Diagram: Introduction to Fuzzy Logic
Superconductive Energy-Efficient Computing - ASC-2014 Plenary-series - 6 of 13 - Wednesday 2014/8/13
Design and Comparison of Crosstalk Circuits at 7nm - Md Arif Iqbal - ICRC San Mateo, 2019
Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic: IEEE Rebooting Computing 2017

IEEE-USA E-Books

  • Novel SOI wafer engineering using low stress and high mobility CMOSFET with <100>-channel for embedded RF/analog applications

    For high performance RF/analog and logic device technology, novel SOI wafer engineering featuring <100>-channel SOI CMOSFET with high-resistivity substrate is proposed. Mobility of PMOSFET is improved about 16% by changing a channel direction from <110> to <100>. Moreover, the reduction of the drive current in narrow channel PMOSFET is suppressed. The maximum oscillation frequency (f/sub max/) for NMOSFET is improved around 7% by changing the buried oxide (BOX) thickness from 400 nm to 150 nm because the self-heating effect is suppressed, and is improved around 5% by changing the substrate resistivity from 10 /spl Omega/cm to 1000 /spl Omega/cm because the power loss is reduced. In this work, the wafer engineering which consists of 1) <100>-channel, 2) optimization of BOX, and 3) high resistivity substrate, is proposed to improve the RF performance of the CMOSFET.

  • A BIST circuit for I/sub DDQ/ tests

    In this paper, an I/sub DDQ/ test time reduction method is proposed which is suitable for BIST approaches. Also, a BIST circuit for I/sub DDQ/ tests, based on the method, is proposed. The layout of a CMOS logic circuit having the BIST circuit is designed and the performance is evaluated by SPICE simulation. The results show us that I/sub DDQ/ test time can be reduced by using this test circuit.

  • Transmission gate-interfaced APDL design

    Based on the recent adiabatic pseudo domino logic (APDL), a new circuit structure, transmission gate-interfaced APDL (T-APDL), is proposed to improve the performance of the APDL circuit, especially for power consumption, operating voltage and frequency characteristics. Although an additional transistor is required in the basic T-APDL structure, the power saving compared to APDL is significant and the proposed circuits have been simulated to function in excess of 400 MHz and as low as 2 V. Both structures have been fully simulated using HSPICE, with 0.8 /spl mu/m, n-well CMOS process parameters, and the results are presented here. The generation of the control signals for the transmission gate (T-gate) is also discussed.

  • EMC issues relating to the design of communicating appliances

    There has been a rapid growth in the use of mobile communications with the emergence of digital radio technologies. In parallel with this PDAs (Personal Digital Assistants) are now starting to enter the market place. The development of commercial products combining both digital electronics and RF (radio frequency) circuits gives rise to some important EMC (electromagnetic compatibility) challenges. These can broadly be categorised into two areas. Does RF interference from the transmitter of the radio cause upset of the digital circuits? Will the sensitivity of a receiver be reduced if it is placed in close proximity to some digital circuitry? This paper reports explorative measurements in both these areas. Comparative measurements of susceptibility of logic gates to RF interference are presented. These results indicate that the use of HC (high speed CMOS) devices can considerably reduce susceptibility to RF interference. In addition measurements have been taken to show how receiver sensitivity can become be degraded when operating in close proximity to digital circuitry.

  • Design of CMOS self-checking sequential circuits with improved detectability of bridging faults

    Problems due to the presence of resistive bridging faults within sequential functional blocks of self-checking circuits are studied, and design criteria aimed at reducing their effects are proposed.<<ETX>>

  • Associating CMOS transistors with BDD arcs for technology mapping

    A novel BDD (binary decision diagram) class that allows a direct association of CMOS transistors with BDD arcs is proposed. This BDD class, terminal suppressed BDDs (TBDDs), allows a direct technology mapping with the aim of automatic leaf cell generation. This is obtained from a straightforward extraction of the cell transistor topology from a TBDD.<<ETX>>

  • VLSI implementation of a low-power antilogarithmic converter

    This paper presents a VLSI implementation of a unique 32-bit antilogarithmic converter, which generates data for some digital-signal-processing (DSP) applications. Novel antilogarithm correcting algorithms are developed and implemented with low-power and hardware-efficient correcting circuits. The VLSI implementations of these algorithms are much smaller than other hardware intensive algorithms found in the literature. The converter is implemented using 0.6 /spl mu/m CMOS technology, and its combinational logic implementation requires 1500/spl lambda//spl times/2800/spl lambda/ of chip area. The 32-bit antilogarithmic converter computes the antilogarithm in a single clock cycle and runs at 100 MHz and consumes 81 mW.

  • Compact four bit carry look-ahead CMOS adder in multi-output DCVS logic

    A four-bit carry look-ahead (CLA) CMOS adder based on transistor sharing in a multi-output differential cascode voltage switch (MODCVS) logic is presented. This adder uses a new enhanced CLA unit, which enables the generation of all output carries in one single compact gate structure. Simulation results using HSPICE with CMOS 1.0 /spl mu/m technology designs show that the four-bit adder proposed has 15.7% less transistors, 27.2% less silicon area, /spl sim/14% speed improvement, and a 29.1% reduction in average power consumption compared to a standard DCVS implementation.

  • High-speed digital circuits for a 2.4 GHz all-digital RF frequency synthesizer in 130 nm CMOS

    We present high-speed digital circuits that comprise the first ever reported all-digital 2.4 GHz frequency synthesizer and transmitter that meet the Bluetooth specifications. The chip is built in a digital 130 nm CMOS process with no analog extensions and features high logic gate density of 150 kgates per mm/sup 2/. The transmitter architecture is based on an all-digital phase- locked loop (AD-PLL), which is built from the ground up using digital techniques that exploit high speed and high density of a deep-submicron CMOS process while avoiding its weaker handling of voltage resolution. We also present a high-performance flip-flop used in this design. It features low CLK- to-Q delay and negative setup time. Because the flip-flop is symmetrical along the vertical axis, the resolution window is symmetrical for rising and falling data transitions in the time-to-digital converter (TDC). The RF transmitter area occupies only 0.54 mm/sup 2/ and the current consumption is 49 mA at 1.5 V supply and 4 mW of RF output, and includes the companion DSP. This proves attractiveness and competitiveness of the "digital RF" approach whose goal is to replace RF functions with high-speed digital logic gates.

  • Sub-quarter-micron dual gate CMOSFETs with ultra-thin gate oxide of 2 nm

    The high performance 0.25 /spl mu/m dual gate CMOS with ultrathin gate oxide of 2 nm is demonstrated for low-voltage logic application. The boron penetration can effectively be suppressed by the nitrogen implantation technique, even if the gate oxide film is reduced to 2 nm. Moreover the inverter delay with an Al interconnect load can be remarkably improved by the highly drivable MOSFETs with thin gate oxide for low-voltage operation. Furthermore, the hot carrier degradation of NMOSFETs can be suppressed as reducing the oxide thickness. However it is found that the hot-carrier degradation of PMOSFETs is enhanced in thin-oxide region under channel hot- hole injection.



Standards related to CMOSFET logic devices

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IEEE Guide for the Application of Faulted Circuit Indicators for 200 / 600 A, Three-phase Underground Distribution

This application guide provides information on what a FCI is designed to do and describes methods for selecting FCIs for three-phase, 200 / 600 amp underground distribution circuits. This application guide will complement the existing single phase application guide.