Conferences related to CMOSFETs

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2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2020 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

EDSSC provides as a multidisciplinary forum for the exchange of ideas, research results, and industry experience in the broad areas of electron devices and solid state circuits and systems. The technical program includes invited talks by famous scientists and contributed papers.


2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

The fifth joint EUROSOI-ULIS event will be hosted by IMEP-LaHC in Grenoble, France. The focus of the sessions is on advanced nanoscale devices, including SOI technology.Papers in the following areas are solicited:-Physical mechanisms and innovative SOI-like devices.-New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.-Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.-New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc. Advanced test structures and characterization techniques, reliability and variability assessment techniques for new materials and novel devices.

  • 2018 Joint International EUROSOI Workshop andInternational Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

    The fourth joint EUROSOI-ULIS event will be hosted by the University of Granada in Granada, Spain. The focus of the sessions is on advanced nanoscale devices, including SOI technology. Papers in the following areas are solicited:Physical mechanisms and innovative SOI-like devices.New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.

  • 2017 Joint International EUROSOI Workshop andInternational Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

    EUROSOI-ULIS is a European Conference that resulted from the merging in 2015 of the two sister Conferences: EUROSOI and ULIS. The aim of the EUROSOI-ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale semiconductor-on-insulator and silicon-compatible devices. Papers related to the More Moore, More than Moore and Beyond CMOS research fields (alternative semiconductor and dielectric materials, innovative devices, circuit and system design, etc) are highly encouraged.

  • 2016 Joint International EUROSOI Workshop andInternational Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

    In order to further increase audience and scientific impact, the two sister conferences ULIS and EUROSOI have decided to merge in 2015 and the first joint EUROSOI-ULIS event was a sucess. The aim of the EUROSOI-ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale semiconductor-on-insulator and silicon-compatible devices. Papers corresponding to the More Moore, More than Moore and Beyond CMOS domains (alternative semiconductor and dielectric materials, innovative devices, circuit and system design, etc) are highly encouraged.

  • 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

    The future landscape of the micro-nano-electronics will essentially contain extremely miniaturized fully depleted devices such as planar SOI or narrow FinFETs and nanowires. These aspects were covered in both ULIS and EuroSOI conferences, leading to significant overlap. In order to further increase audience and scientific impact, the two sister conferences have decided to merge in 2015. The aim of the EUROSOI-ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale semiconductor-on-insulator and silicon-compatible devices. Papers corresponding to the More Moore, More than Moore and Beyond CMOS domains (alternative semiconductor and dielectric materials, innovative devices, circuit and system design, etc) are highly encouraged.

  • 2014 15th International Conference on Ultimate Integration on Silicon (ULIS)

    The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modelling, simulation and characterisation of advanced nanoscale silicon and silicon compatible devices for More Moore (CMOS, Memories), More than Moore (Nanosensing, Energy Harvesting, RF, ...) and Beyond-CMOS (Nanowires, CNT, Graphene, Tunnel FET, ...) applications.

  • 2013 14th International Conference on Ultimate Integration on Silicon (ULIS)

    The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modelling, simulation and characterisation of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.

  • 2012 13th International Conference on Ultimate Integration on Silicon (ULIS)

    The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modelling, simulation and characterisation of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.

  • 2011 12th International Conference on Ultimate Integration on Silicon (ULIS)

    ULIS is an annual conference that regroups the European research community working on advanced silicon devices and nanodevices. It has been held annually since 2000. The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modelling, simulation and characterisation of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.

  • 2009 10th International Conference on Ultimate Integration on Silicon (ULIS)

    The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.

  • 2008 9th International Conference on Ultimate Integration on Silicon (ULIS)

    The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale silicon and silicon compatible devices for switches, memory and novel applications such as sensors and bioelectronics.


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Periodicals related to CMOSFETs

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Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Electron Devices, IEEE Transactions on

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronics devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


Instrumentation and Measurement, IEEE Transactions on

Measurements and instrumentation utilizing electrical and electronic techniques.


Microwave and Wireless Components Letters, IEEE

Published monthly with the purpose of providing fast publication of original and significant contributions relevant to all aspects of microwave/millimeter-wave technology. Emphasis is on devices, components, circuits, guided-wave structures, systems and applications covering the frequency spectrum from microwave and beyond, including submillimeter-waves and infrared.


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Xplore Articles related to CMOSFETs

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Integration of ultrathin (1.6/spl sim/2.0 nm) RPECVD oxynitride gate dielectrics into dual poly-Si gate submicron CMOSFETs

International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), 1999

Detailed comparisons indicates superior performance and reliability in dual poly-Si gate CMOSFETs in which oxynitride alloys have been substituted for nitrides of stacked oxide/nitride dielectrics with Tox-eq /spl sim/2 nm. Similar comparisons using CMOSFETs with optimized oxide/oxynitride stacked dielectrics (Tox-eq /spl sim/1.67 nm) which also include interface plasma- nitridation at the one monolayer level are reported. These also indicate superior ...


Characterization of Near-Interface Oxide Trap Density in Nitrided Oxides for Nanoscale MOSFET Applications

IEEE Transactions on Nanotechnology, 2009

This paper presents the depth profile of oxide trap density, extracted from the dual gate processed thermally grown oxide in NO ambient and remote plasma nitrided oxides by using multifrequency and multitemperature charge pumping technique in conjunction with the tunneling model of trapped charges. Nitrided oxide is widely used to improve the reliability of nanoscale MOSFETs because it can decrease ...


Insight into the S/D engineering by high-resolution imaging and precise probing of 2D-carrier profiles with scanning spreading resistance microscopy

2009 IEEE International Electron Devices Meeting (IEDM), 2009

For the first time, high-resolution carrier imaging has been carried out on (110)/(100) pFETs and nFETs with scanning spreading resistance microscopy (SSRM). The S/D of (110) pFETs shows less lateral distribution than that of (100), strongly indicating 2D-channeling effect of boron I/I. Direct evidence has been shown that As out-diffusion under NiSi made conductive paths that degrade junction leakage on ...


Experimental study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5 nm

Digest. International Electron Devices Meeting,, 2002

The electrical characteristics of ultrathin-body SOI CMOSFETs with SOI thickness ranging from 2.3 nm to 8 nm are intensively investigated. As a result, it is demonstrated, for the first time, that electron mobility increases as SOI thickness decreases, when SO, thickness is in the range from 3.5 nm to 4.5 nm. In addition, it is demonstrated that, when SOI thickness ...


Back-channel effect on SOI CMOS for high voltage power ICs

Proceedings of 9th International Symposium on Power Semiconductor Devices and IC's, 1997

Silicon On Insulator (SOI) technology is becoming very attractive for power ICs because CMOS controlled circuits and high voltage devices can be integrated on a single die. For applications such as inverters for electronic ballast, motor control and power source, the CMOSFETs and power devices are required to operate in high-side mode. Recently, it has been shown that power devices ...


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Educational Resources on CMOSFETs

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IEEE.tv Videos

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IEEE-USA E-Books

  • Integration of ultrathin (1.6/spl sim/2.0 nm) RPECVD oxynitride gate dielectrics into dual poly-Si gate submicron CMOSFETs

    Detailed comparisons indicates superior performance and reliability in dual poly-Si gate CMOSFETs in which oxynitride alloys have been substituted for nitrides of stacked oxide/nitride dielectrics with Tox-eq /spl sim/2 nm. Similar comparisons using CMOSFETs with optimized oxide/oxynitride stacked dielectrics (Tox-eq /spl sim/1.67 nm) which also include interface plasma- nitridation at the one monolayer level are reported. These also indicate superior performance and reliability with respect to CMOSFET devices with stacked oxide/nitride dielectrics, including an additional /spl sim/10/spl times/ decrease in direct tunneling due to the interface nitridation.

  • Characterization of Near-Interface Oxide Trap Density in Nitrided Oxides for Nanoscale MOSFET Applications

    This paper presents the depth profile of oxide trap density, extracted from the dual gate processed thermally grown oxide in NO ambient and remote plasma nitrided oxides by using multifrequency and multitemperature charge pumping technique in conjunction with the tunneling model of trapped charges. Nitrided oxide is widely used to improve the reliability of nanoscale MOSFETs because it can decrease the degradation of gate oxide due to the generation of traps therein. Based on the measurement, the optimum nitrogen concentration in such typical nitrided process is discussed in correlation with the gate oxide thickness for nanoscale CMOSFETs.

  • Insight into the S/D engineering by high-resolution imaging and precise probing of 2D-carrier profiles with scanning spreading resistance microscopy

    For the first time, high-resolution carrier imaging has been carried out on (110)/(100) pFETs and nFETs with scanning spreading resistance microscopy (SSRM). The S/D of (110) pFETs shows less lateral distribution than that of (100), strongly indicating 2D-channeling effect of boron I/I. Direct evidence has been shown that As out-diffusion under NiSi made conductive paths that degrade junction leakage on (110) nFETs. The Si:C influences on S/D profiles are also directly observed. We also succeeded in a full-FIB sample-making for the first time, showing the high potential of SSRM technology for further scaled devices.

  • Experimental study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5 nm

    The electrical characteristics of ultrathin-body SOI CMOSFETs with SOI thickness ranging from 2.3 nm to 8 nm are intensively investigated. As a result, it is demonstrated, for the first time, that electron mobility increases as SOI thickness decreases, when SO, thickness is in the range from 3.5 nm to 4.5 nm. In addition, it is demonstrated that, when SOI thickness is thinner than 4 nm, slight (even atomic-level) SOI thickness fluctuations have a significant impact on threshold voltage, gate-channel capacitance, and carrier mobility of ultrathin-body CMOSFETs.

  • Back-channel effect on SOI CMOS for high voltage power ICs

    Silicon On Insulator (SOI) technology is becoming very attractive for power ICs because CMOS controlled circuits and high voltage devices can be integrated on a single die. For applications such as inverters for electronic ballast, motor control and power source, the CMOSFETs and power devices are required to operate in high-side mode. Recently, it has been shown that power devices in SOI substrate with silicon thickness (t/sub SOI/) of around 1 /spl mu/m have excellent characteristics. The back-gate-bias effects on SOI Lateral DMOSFET (LDMOS) and ultra-thin SOI CMOS have also been reported. However, there has been no report studying the leakage characteristics of SOI CMOS with silicon thickness of around 1 /spl mu/m under a very large negative back gate bias typical of high-side operations. In this paper, we present such back- channel effect on SOI CMOS. The possible solutions are discussed with numerical simulation results.

  • Comparative Scalability of PVD and CVD TiN on HfO2 as a Metal Gate Stack for FDSOI cMOSFETs down to 25nm Gate Length and Width

    This paper compares, for the first time, the scalability of physical- and chemical-vapor-deposited (PVD and CVD) TiN on HfO<sub>2 </sub> as a gate stack for FDSOI cMOSFETs down to 25nm gate length and width. It is shown that not only the intrinsic material properties but also the device architecture strongly influences the final gate stack properties. Reliability issues, stress and gate control in the sub-35nm scale are reported and explained, thanks to material, electric data and mechanical simulations. In spite of its lower performance on large device dimensions, PVD-TiN demonstrates a better overall trade-off, leading to a 17% ion improvement on 25nm short and narrow devices

  • Issues and optimization of millisecond anneal process for 45 nm node and beyond

    We have investigated millisecond anneal, such as laser spike annealing (LSA) and flash lamp annealing (FLA), which substitute for spike RTA as a dopant activation technology of source/drain extension for 45 nm node. Three key issues of gate leakage current, junction leakage current and pattern dependence were discussed from the integration and CMOSFETs performance viewpoint. We reported that LSA is the leading candidate for 45 nm node and beyond.

  • Performance and structures of scaled-down bipolar devices merged with CMOSFETs

    Fabricating BiCMOS test samples, performance and structures of 2 &#181;m and scaled BiCMOS are evaluated. The developed BiCMOS processes realize almost the same device characteristics of bipolar and CMOS LSIs fabricated with the same lithographic technology. The intrinsic delays of BiCMOS and CMOS 2-NAND circuits are 0.5 ns and 0.4 ns respectively. The delay times are comparable with the bipolar ECL circuits. The BiCMOS technology makes it possible to fabricate high-speed, low-power dissipation, high-packing density LSIs by sharing the roles among them.

  • Correlating drain-current with strain-induced mobility in nanoscale strained CMOSFETs

    The correlation between channel mobility gain (Deltamu), linear drain-current gain (DeltaI<sub>dlin</sub>), and saturation drain-current gain (DeltaIdsat) of nanoscale strained CMOSFETs are reported. From the plots of DeltaI<sub>dlin</sub> versus DeltaI<sub>dsat</sub> and ballistic efficiency (Bsat,PSS), the ratio of source/drain parasitic resistance (R<sub>SD,PSS</sub>) to channel resistance (R<sub>CH,PSS</sub>) of strained CMOSFETs can be extracted. By plotting Deltamu versus DeltaI<sub>dlin</sub>, the efficiency of Deltamu translated to DeltaI<sub>dlin</sub> is higher for strained pMOSFETs than strained nMOSFETs due to smaller RSD,PSS-to-RCH,PSS ratio of strained pMOSFETs. It suggests that to exploit strain benefits fully, the RSD,PSS reduction for strained nMOSFETs is vital, while for strained pMOSFETs the DeltaI<sub>dlin </sub>-to-Deltamu sensitivity is maintained until R<sub>SD,PSS</sub> becomes comparable to/or higher than R<sub>CH,PSS</sub>

  • HfSiON gate dielectric for CMOS applications

    In this paper, we review our results on HfSiON deposited by MOCVD. Characteristics of capacitors and FETs fabricated by the conventional poly-Si gate CMOS process are discussed. We cover the issues of flatband voltage shift, effective inversion-layer mobility in relation to fabrication method of HfSiON, design consideration of HfSiON for 50 nm CMOSFETs and dielectric reliability.



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