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The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.
The IEEE International Microwave Symposium (IMS) is the world s foremost conference covering the UHF, RF, wireless, microwave, millimeter-wave, terahertz, and optical frequencies; encompassing everything from basic technologies to components to systems including the latest RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation and more. The IMS includes technical and interactive sessions, exhibits, student competitions, panels, workshops, tutorials, and networking events.
The world's premiere conference in MEMS sensors, actuators and integrated micro and nano systems welcomes you to attend this four-day event showcasing major technological, scientific and commercial breakthroughs in mechanical, optical, chemical and biological devices and systems using micro and nanotechnology.The major areas of activity in the development of Transducers solicited and expected at this conference include but are not limited to: Bio, Medical, Chemical, and Micro Total Analysis Systems Fabrication and Packaging Mechanical and Physical Sensors Materials and Characterization Design, Simulation and Theory Actuators Optical MEMS RF MEMS Nanotechnology Energy and Power
The DATE conference addresses all aspects of research into technologies for electronic andembedded system engineering. It covers the design process, test, and automation tools forelectronics ranging from integrated circuits to distributed embedded systems. This includes bothhardware and embedded software design issues. The conference scope also includes theelaboration of design requirements and new architectures for challenging application fields suchas telecoms, wireless communications, multimedia, healthcare, smart energy and automotivesystems. Companies also present innovative industrial designs to foster the feedback fromrealworld design to research. DATE also hosts a number of special sessions, events within themain technical programme such as panels, hot-topic sessions, tutorials and workshopstechnical programme such as panels, hot-topic sessions, tutorials and workshops.
Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...
This publication covers the theory, design, fabrication, manufacturing and application of information displays and aspects of display technology that emphasize the progress in device engineering, device design, materials, electronics, physics and reliabilityaspects of displays and the application of displays.
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
Electronics Letters, 2008
IEEE Transactions on Nanotechnology, 2003
The drain current-voltage (I-V) characteristics of Schottky-barrier carbon nanotube field-effect transistors (FETs) are computed via a self-consistent solution to the two-dimensional potential profile, the electron and hole charges in the nanotube, and the electron and hole currents. These out-of- equilibrium results are obtained by allowing splitting of both the electron and hole quasi-Fermi levels to occur at the source and ...
2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 2017
Emerging applications require computing platforms to extract task-relevant information from increasingly large amounts of data. These requirements place stringent constraints on energy efficiency, throughput, latency, and for certain data types, security and privacy of computing platforms. Traditionally, silicon CMOS scaling has been relied upon to meet these energy and delay constraints. However, the energy and delay benefits achievable via scaling ...
Recent Advances in Space Technology Services and Climate Change 2010 (RSTS & CC-2010), 2010
In this paper, we have proposed the compact modeling of ballistic CNTFET and the performance analysis of the developed model using various characteristics. The carbon nanotube transistors (CNTFET) are currently considered and most promising component to replace the generation of MOSFET transistor, especially in order to surpass the short channel effects in the component. For this new generation of transistor ...
Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC., 2004
In this paper, we have succeeded in observing the coexistence of the Coulomb charging effect and the coherent transport of holes in a carbon nanotube of length 4.5 /spl mu/m at 8.6 K. A back gate type carbon nanotube field effect transistor was fabricated for this purpose. The drain current-gate voltage characteristics, Coulomb diamond characteristics, and periodic negative differential conductance ...
The drain current-voltage (I-V) characteristics of Schottky-barrier carbon nanotube field-effect transistors (FETs) are computed via a self-consistent solution to the two-dimensional potential profile, the electron and hole charges in the nanotube, and the electron and hole currents. These out-of- equilibrium results are obtained by allowing splitting of both the electron and hole quasi-Fermi levels to occur at the source and drain contacts to the tube, respectively. The interesting phenomena of bipolar conduction in a FET, and of drain-induced barrier thinning (DIBT) are observed. These phenomena are shown to add a breakdown-like feature to the drain I-V characteristic. It is also shown that a more traditional, saturating-type characteristic can be obtained by workfunction engineering of the source and drain contacts.
Emerging applications require computing platforms to extract task-relevant information from increasingly large amounts of data. These requirements place stringent constraints on energy efficiency, throughput, latency, and for certain data types, security and privacy of computing platforms. Traditionally, silicon CMOS scaling has been relied upon to meet these energy and delay constraints. However, the energy and delay benefits achievable via scaling are diminishing. Increased vulnerability to various sources of variations (e.g., process, voltage) further exacerbates these energy and speed challenges.
In this paper, we have proposed the compact modeling of ballistic CNTFET and the performance analysis of the developed model using various characteristics. The carbon nanotube transistors (CNTFET) are currently considered and most promising component to replace the generation of MOSFET transistor, especially in order to surpass the short channel effects in the component. For this new generation of transistor (CNTFET) with very short channel, the majority of models describing electrical conduction based on the process of ballistic transport. We propose design-oriented compact models for ballistic CNTFET. We are interested more particularly to the drain current and the quantum capacitance as a function of the gate voltage (VGS), for various values of the nanotube diameter and the oxide thickness. These models have been simulated and the results that are obtained were in excellent agreement with the theoretical calculations.
In this paper, we have succeeded in observing the coexistence of the Coulomb charging effect and the coherent transport of holes in a carbon nanotube of length 4.5 /spl mu/m at 8.6 K. A back gate type carbon nanotube field effect transistor was fabricated for this purpose. The drain current-gate voltage characteristics, Coulomb diamond characteristics, and periodic negative differential conductance were measured. Results confirm the coexistence of the Coulomb charging effect and ballistic transport of the holes in semiconductive carbon nanotubes.
In this paper, we propose a two-port network model of a single walled (SW) carbon nanotube field effect transistor (CNT-FET) which includes contacts for analyzing S-parameter measurement results. The radio frequency (RF) transmission properties of single walled CNT-FETs have been characterized up to 12 GHz using the proposed two-port network model. The analytical results are in good agreement with the published experimental results.
This paper investigates the performance of Single Edge Triggered D-Flip flop (SET D-FF) using Carbon Nanotube Field Effect Transistors (CNFETs). The circuit performance of CNFET model has been compared with that of silicon based MOSFET model. CNFET circuit models are tested for various substrate bias voltages in sub threshold region. A 10 Transistor version of SET D-FF is implemented using PTM 32nm CMOS model and Stanford single-walled CNFET model and simulated using HSPICE. The performance parameter under investigation is Power Delay Product (PDP). The comparative simulation result at various frequencies show that CNFET SET DFFs have superior Power Delay Product over MOSFET SET DFFs.
In this letter, we propose a semiclassical model for the performance investigation and optimization of the double-gate carbon nanotube field-effect transistor (DG-CNTFET). The DG-CNTFET is effective in controlling the ambipolar conduction that is inherent to Schottky barrier (SB) CNTFETs using two independent gates, namely, the primary gate and the polarity gate. Whereas the primary gate serves to turn the device on and off, the polarity gate can be used to configure the device in either the p-type or the n-type mode of operation. The DG-CNTFET exhibits unipolar conduction and can achieve a large ratio of over six orders of magnitude. Since the proposed model is physics based and does not rely on fitting parameters, it can be used to study the effect of parameters such as CNT chirality, SB height, and gate dielectric thickness on the DG-CNTFET performance.
Nanoscale devices in near future are going to be less than the mean free path of carriers. The ballistic conduction is highly probable in these devices. We have investigated the physics of the ballistic field effect transistors (FETs). The I-V characteristics of the ballistic silicon MOSFET is shown, and the mechanism of device operation was discussed. The performance limit of the MOSFET is discussed by means of the ballistic MOSFET characteristics derived. Performance of the experimental device is compared to the ballistic limit in some fabricated samples. The carbon nanotube FET is introduced as the other example of the ballistic FET. The device was found to be of exceedingly high performance if the ballistic conduction was actually realized.
As the technology scales down to 32nm or below, the leakage power starts dominating the total power. Reduction of this leakage problem is the major problem, today's CMOS technology is facing. Hence researchers are looking for alternate technologies. The Carbon Nanotubes FET (CNTFET) is found to be a most promising device that becomes alternative or replacement for present CMOS technology. As the full adder is one of the major units of the ALU, it plays important role in speed and power consumption. In this paper several CNTFET full adder circuits are designed by applying different leakage power reduction techniques to reduce leakage power and to enhance the performance of the full adder circuit. Finally the full adder circuit with the proposed stacked single transistor leakage feedback technique was designed and proved that the proposed stacked single transistor leakage feedback CNTFET Full adder will reduce more leakage power with the same performance compared to all other techniques.
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