Conferences related to Capacitance-voltage characteristics

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2020 IEEE Applied Power Electronics Conference and Exposition (APEC)

APEC focuses on the practical and applied aspects of the power electronics business. Not just a power designer’s conference, APEC has something of interest for anyone involved in power electronics including:- Equipment OEMs that use power supplies and converters in their equipment- Designers of power supplies, dc-dc converters, motor drives, uninterruptable power supplies, inverters and any other power electronic circuits, equipments and systems- Manufacturers and suppliers of components and assemblies used in power electronics- Manufacturing, quality and test engineers involved with power electronics equipment- Marketing, sales and anyone involved in the business of power electronic- Compliance engineers testing and qualifying power electronics equipment or equipment that uses power electronics


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2020 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)

The Conference focuses on all aspects of instrumentation and measurement science andtechnology research development and applications. The list of program topics includes but isnot limited to: Measurement Science & Education, Measurement Systems, Measurement DataAcquisition, Measurements of Physical Quantities, and Measurement Applications.


2020 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


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Periodicals related to Capacitance-voltage characteristics

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Dielectrics and Electrical Insulation, IEEE Transactions on

Electrical insulation common to the design and construction of components and equipment for use in electric and electronic circuits and distribution systems at all frequencies.


Display Technology, Journal of

This publication covers the theory, design, fabrication, manufacturing and application of information displays and aspects of display technology that emphasize the progress in device engineering, device design, materials, electronics, physics and reliabilityaspects of displays and the application of displays.


Electron Device Letters, IEEE

Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.


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Most published Xplore authors for Capacitance-voltage characteristics

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Xplore Articles related to Capacitance-voltage characteristics

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A Consistent Parameter Extraction Method for Deep Submicron MOSFETs

27th European Solid-State Device Research Conference, 1997

None


Simulation-based assessment of 50 nm double-gate SOI CMOS performance

1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199), 1998

Scaling CMOS to sub-0.1 /spl mu/m is a formidable task, irrespective of the particular technology. Bulk-Si devices require complex channel doping variations to control short-channel effects (SCEs). Partially depleted SOI devices also require such doping, and they involve additional design consideration of the (good and bad) floating-body effects. Conventional fully depleted (FD) SOI devices are scalable only to /spl sim/0.2 ...


The mechanism of schottky-barrier formation in poly-p-phenylene

1991 Annual Report. Conference on Electrical Insulation and Dielectric Phenomena,, 1991

The temperature dependence of the capacitance and current-voltage characteristics of Al/PPP junction device has been measured in order to investigate the junction properties. The barrier height and the effective Richardson constant of the junction have been determined to be 0.48 eV and 1.2x1/sup -4/Acm/sup -2/K/sup -1/ by Richardson plots. Analysis of the metal- polymer interface by x-ray photoemission spectroscopy (XPS) ...


Investigation of the characteristics of the junction between n-Si and the poly(dithienopyrrole)-polyvinylchloride composite

International Conference on Science and Technology of Synthetic Metals, 1994

None


A simple physical comparison of amplifying devices of the emitter-control-collector variety: A survey

1959 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1959

None


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Educational Resources on Capacitance-voltage characteristics

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IEEE-USA E-Books

  • A Consistent Parameter Extraction Method for Deep Submicron MOSFETs

    None

  • Simulation-based assessment of 50 nm double-gate SOI CMOS performance

    Scaling CMOS to sub-0.1 /spl mu/m is a formidable task, irrespective of the particular technology. Bulk-Si devices require complex channel doping variations to control short-channel effects (SCEs). Partially depleted SOI devices also require such doping, and they involve additional design consideration of the (good and bad) floating-body effects. Conventional fully depleted (FD) SOI devices are scalable only to /spl sim/0.2 /spl mu/m. However, double-gate (DG) FD/SOI devices seem to be special; Monte Carlo simulations have shown them to have excellent characteristics at the lateral or 2D integration scaling limit of /spl sim/30 nm (Frank et al. IEEE IEDM Tech. Dig., p. 553, 1992). Ideally, the DG/SOI MOSFET, with the two gates electrically coupled through the thin SOI film, offers good control of SCEs even with uniform and very low film/channel doping, high drive current and transconductance due to the gate coupling and the inherent high carrier mobility, low off-current with low threshold voltage because of the nearly ideal subthreshold slope, and other unique features shown herein. The downside of DG/CMOS is the complex processing needed to fabricate the "near-ideal" devices. A poignant question then is how near ideal must the devices be for their unique features to significantly benefit real scaled circuits. In this paper, we provide insight to this question via a simulation-based study of 50 nm DG/SOI CMOS devices and circuits.

  • The mechanism of schottky-barrier formation in poly-p-phenylene

    The temperature dependence of the capacitance and current-voltage characteristics of Al/PPP junction device has been measured in order to investigate the junction properties. The barrier height and the effective Richardson constant of the junction have been determined to be 0.48 eV and 1.2x1/sup -4/Acm/sup -2/K/sup -1/ by Richardson plots. Analysis of the metal- polymer interface by x-ray photoemission spectroscopy (XPS) technique shows that an aluminum oxide complex is formed at the interface which would be the origin of the contact effects. The small effective Richardson constant has been due to existence of that composite layer, acting as a tunneling one.

  • Investigation of the characteristics of the junction between n-Si and the poly(dithienopyrrole)-polyvinylchloride composite

    None

  • A simple physical comparison of amplifying devices of the emitter-control-collector variety: A survey

    None

  • Errata

    None

  • Photovoltaic properties of Cu(In,Ga)Se/sub 2/ thin film solar cell fabricated by coevaporation process

    Thin film solar cells based on Cu(In,Ga)Se/sub 2/ films were fabricated, and their junction and photovoltaic properties were investigated. Ga in CuInSe/sub 2/ thin films formed by the so-called "bilayer process" was incorporated homogeneously. The fabricated cell structure was glass/Mo/Cu(In,Ga)Se/sub 2//CdS/ZnO/ITO(/MgF/sub 2/). The incorporation of Ga into CuInSe/sub 2/ films up to about 20 mol% improved the photovoltaic performance. From the study of photoluminescence, capacitance-voltage and current-voltage characteristics, it was clarified that the incorporation of Ga not only widened the bandgap energy, but also played an important role in the effect which yields hole concentration. The best cell with an AR-coating (MgF/sub 2/) exhibited an efficiency of 15.2%; Jsc=33.9 mA/cm/sup 2/, Voc=0.616 V, FF=0.730. The device performance can be improved by the development of the film with higher hole concentration, keeping the crystalline quality.

  • The influence of material structure of thick film resistor on C-V characteristic

    The materials for thick film resistive layers are inhomogeneous mixtures. The layers contain particles of conductive functional component (in this case, carbonic) dissipated in an insulative matrix. The current-voltage characteristics of resistors prepared by thick film technology are nonlinear. The deviation from linearity of the C-V characteristic may have contributions from both the resistive layer material and the contact-resistive layer interface. The object of this work was the investigation of the influence of these two systems, the resistive layer and the resistive layer/contact interface, with regard to their influence on the nonlinearity. Measurement of third harmonic voltage was used for determination of nonlinearity of the C-V characteristic, as direct measurement of the C-V characteristic does not enable discovery of the small linearity deviation of the C-V characteristic. The samples were powered by a pure sinusoidal signal. The pure sinusoidal signal was distorted by transit through layer and interface inhomogeneity. For investigation, sample resistors with different size (width and length) were used. The third harmonics measurement was performed on samples powered by a signal with constant current density and constant current.

  • Electrical properties of porous silicon stabilised by storage in ambient

    The electrical transport of stabilised porous silicon layers was investigated. The samples were stored in ambient for 1.5-2 years. A MIS-like C-V characteristic, a strong rectifying I-V curve and I-T dependence with two activation energies were obtained. Thermally stimulated depolarisation currents have an activation energy of 0.81-0.87 eV. The electrical properties are discussed in the frame of a quantum confinement model, keeping into account the surface component.

  • Germanium pMOSFET with HfON gate dielectric

    In this paper, we study about the electrical performance of Ge MOSFET with a thin HfO/sub x/N/sub y/ gate dielectrics. The capacitance-voltage and gate leakage current-voltage characteristics of HfON Ge MOS capacitor was discussed. Sheet resistances are reduced with increasing the annealing temperatures from 360/spl deg/C to 650/spl deg/C. Effective carrier mobility of Ge MOSFET was extracted by measuring the gate oxide capacitance and inversion charge. The transconductance and the transfer curves of Ge MOSFET was analysed at room temperature.



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