Conferences related to Circuit Optimization

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2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


2020 IEEE International Conference on Systems, Man, and Cybernetics (SMC)

The 2020 IEEE International Conference on Systems, Man, and Cybernetics (SMC 2020) will be held in Metro Toronto Convention Centre (MTCC), Toronto, Ontario, Canada. SMC 2020 is the flagship conference of the IEEE Systems, Man, and Cybernetics Society. It provides an international forum for researchers and practitioners to report most recent innovations and developments, summarize state-of-the-art, and exchange ideas and advances in all aspects of systems science and engineering, human machine systems, and cybernetics. Advances in these fields have increasing importance in the creation of intelligent environments involving technologies interacting with humans to provide an enriching experience and thereby improve quality of life. Papers related to the conference theme are solicited, including theories, methodologies, and emerging applications. Contributions to theory and practice, including but not limited to the following technical areas, are invited.


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.


2020 Optical Fiber Communications Conference and Exhibition (OFC)

The Optical Fiber Communication Conference and Exhibition (OFC) is the largest global conference and exhibition for optical communications and networking professionals. For over 40 years, OFC has drawn attendees from all corners of the globe to meet and greet, teach and learn, make connections and move business forward.OFC attracts the biggest names in the field, offers key networking and partnering opportunities, and provides insights and inspiration on the major trends and technology advances affecting the industry. From technical presentations to the latest market trends and predictions, OFC is a one-stop-shop.



Periodicals related to Circuit Optimization

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Advanced Packaging, IEEE Transactions on

The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.


Antennas and Propagation, IEEE Transactions on

Experimental and theoretical advances in antennas including design and development, and in the propagation of electromagnetic waves including scattering, diffraction and interaction with continuous media; and applications pertinent to antennas and propagation, such as remote sensing, applied optics, and millimeter and submillimeter wave techniques.


Automatic Control, IEEE Transactions on

The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...



Most published Xplore authors for Circuit Optimization

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Xplore Articles related to Circuit Optimization

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On optimal structure of control vector for analog circuit optimization

2013 12th International Conference on the Experience of Designing and Application of CAD Systems in Microelectronics (CADSM), 2013

The circuit optimization process is formulated as a dynamic controllable system. A special control vector is defined to redistribute the compute expense between a network analysis and a parametric optimization. This redistribution permits the minimization a computer time. The problem of a minimal-time circuit optimization can be formulated in this case as a classical problem of the optimal control for ...


Circuit optimization algorithms for real-time spectrum sharing between radar and communications

2016 IEEE Radar Conference (RadarConf), 2016

The ability of radar and communication applications to share the radio spectrum will require the use of innovative agile circuit techniques for radar and communications. Reconfigurable circuits can provide real-time adjustment of operating frequency and spectral output, while maintaining system performance and maximizing power efficiency. This paper discusses recent developments in circuit optimization techniques for power efficiency and spectral performance. ...


COST: Circuit Optimization SysTem in ASIC library development environment

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), 1999

Increased focus on high performance circuit design and shorter development cycle time for ASIC libraries, are driving the need for automatic circuit optimizers in the ASIC library development environment. High performance input/output circuits are the key differentiator cells in the ASIC library market. Automating the design process of these circuits using an optimizer, not only ensures high performance cells but ...


JiffyTune: circuit optimization using time-domain sensitivities

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998

Automating the transistor and wire-sizing process is an important step toward being able to rapidly design high-performance, custom circuits. This paper presents a circuit optimization tool that automates the tuning task by means of state-of-the-art nonlinear optimization. It makes use of a fast circuit simulator and a general-purpose nonlinear optimization package. It includes minimax and power optimization, simultaneous transistor and ...


Noise considerations in circuit optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000

Noise can cause digital circuits to switch incorrectly, producing spurious results. It can also have adverse power, timing and reliability effects. Dynamic logic is particularly susceptible to charge-sharing and coupling noise. Thus, the design and optimization of a circuit should take noise considerations into account. Such considerations are typically stated as semi- infinite constraints in the time-domain. Semi-infinite problems are ...



Educational Resources on Circuit Optimization

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IEEE-USA E-Books

  • On optimal structure of control vector for analog circuit optimization

    The circuit optimization process is formulated as a dynamic controllable system. A special control vector is defined to redistribute the compute expense between a network analysis and a parametric optimization. This redistribution permits the minimization a computer time. The problem of a minimal-time circuit optimization can be formulated in this case as a classical problem of the optimal control for some functional minimization. The conception of the Lyapunov function of dynamic controllable system is used to analyze the principal characteristics of the process of designing. The analysis of the Lyapunov function and its time derivative gives us a possibility to predict the optimal structure of the control vector and to construct the quasi optimal algorithm of circuit designing.

  • Circuit optimization algorithms for real-time spectrum sharing between radar and communications

    The ability of radar and communication applications to share the radio spectrum will require the use of innovative agile circuit techniques for radar and communications. Reconfigurable circuits can provide real-time adjustment of operating frequency and spectral output, while maintaining system performance and maximizing power efficiency. This paper discusses recent developments in circuit optimization techniques for power efficiency and spectral performance. Optimization of a single parameter (load reflection coefficient) for multiple criteria is first addressed, followed by multiple- parameter, multiple-criteria optimizations. The use of the recently innovated Smith Tube to optimize additional parameters, such as input power and bias voltage, simultaneously with the load impedance is discussed. Optimization examples and a forward look to fast, emerging multidimensional circuit optimization techniques are provided.

  • COST: Circuit Optimization SysTem in ASIC library development environment

    Increased focus on high performance circuit design and shorter development cycle time for ASIC libraries, are driving the need for automatic circuit optimizers in the ASIC library development environment. High performance input/output circuits are the key differentiator cells in the ASIC library market. Automating the design process of these circuits using an optimizer, not only ensures high performance cells but also provides faster design cycle. COST has been used to optimize cells in the development of many ASIC libraries. In this paper we have described the essential components of the COST optimization system and presented a method for optimizing I/O circuits. We have compared the performance of the two cost function heuristics implemented in our optimization system on ASIC input/output circuits.

  • JiffyTune: circuit optimization using time-domain sensitivities

    Automating the transistor and wire-sizing process is an important step toward being able to rapidly design high-performance, custom circuits. This paper presents a circuit optimization tool that automates the tuning task by means of state-of-the-art nonlinear optimization. It makes use of a fast circuit simulator and a general-purpose nonlinear optimization package. It includes minimax and power optimization, simultaneous transistor and wire tuning, general choices of objective functions and constraints, and recovery from nonworking circuits. In addition, the tool makes use of designer-friendly interfaces that automate the specification of the optimization task, the running of the optimizer, and the back-annotation of the results of optimization onto the circuit schematic. Particularly for large circuits, gradient computation is usually the bottleneck in the optimization procedure. In addition to traditional adjoint and direct methods, we use a technique called the adjoint Lagrangian method, which computes all the gradients necessary for one iteration of optimization in a single adjoint analysis. This paper describes the algorithms and the environment in which they are used and presents extensive circuit optimization results. A circuit with 6900 transistors, 4128 tunable transistors, and 60 independent parameters was optimized in about 108 min of CPU time on an IBM RISC/System 6000, model 590.

  • Noise considerations in circuit optimization

    Noise can cause digital circuits to switch incorrectly, producing spurious results. It can also have adverse power, timing and reliability effects. Dynamic logic is particularly susceptible to charge-sharing and coupling noise. Thus, the design and optimization of a circuit should take noise considerations into account. Such considerations are typically stated as semi- infinite constraints in the time-domain. Semi-infinite problems are generally harder to solve than standard nonlinear optimization problems. Moreover, the number of noise constraints can potentially be very large. This paper describes a novel and practical method for incorporating realistic noise considerations during automatic circuit optimization by representing semi- infinite constraints as ordinary equality constraints involving time integrals. Using an augmented Lagrangian optimization merit function, the adjoint method is applied to compute all the gradients required for optimization in a single adjoint analysis, no matter how many noise measurements are considered and irrespective of the dimensionality of the problem. Thus, for the first time, a method is described to practically accommodate a large number of noise considerations during circuit optimization. The technique has been applied to optimization using time-domain simulation, but could be applied in the future to optimization on a static- timing basis. Numerical results are presented.

  • Modeling layout effects for sensitivity-based analog circuit optimization

    Successful deep-submicron designs require significant computation resources for thorough signal and design integrity analysis. Rising quality expectations and shortening time-to-market requirements present additional challenges for design closure. Conventional analog circuit optimizers are efficient in circuit analysis and optimization. Due to recent promising results, designers are beginning to adopt automated physical synthesis in their condensed development cycles in order to improve their prototyping efficiency. For high- performance circuit optimization, idealized performance as well as parasitic data should also be considered. This paper presents an effective framework to incorporate parasitic effects into a sensitivity-based circuit optimization tool. To relieve the physical synthesis bottleneck, estimations of parasitic values based on past extraction results are made during incremental design changes. Sensitivities of the performance impact can then be computed efficiently. As a result physical performance can be optimized using available optimizer and synthesis tools without the need of a priori expert rules, knowledge or cell libraries.

  • Lyapunov function analysis for different strategies of circuit optimization

    The problem of optimization of analog circuit for a minimal computer time has been formulated as the functional minimization problem of the control theory. The process of circuit optimization is formulated as the controllable dynamic system. The conception of the Lyapunov function was proposed to analyze the behavior of the process of circuit optimization. The special function that is a combination of the Lyapunov function and its time derivative was proposed to predict the design time of any strategy. This approach gives us the possibility to select the best strategy from the complete structural basis analyzing the initial part of the total optimization process only.

  • Sensing circuit optimization using different type of transistors for deep submicron STT-RAM

    In this paper, we propose an optimal combination of transistor types in the conventional sensing circuit. A sensing margin, which determines the read yield of STT-RAM, is sensitive to the V<sub>th</sub> type of several transistors in the sensing circuit. Thus, the optimization of the sensing circuit using different types of transistors is important for designing the sensing circuit in STT-RAM. Using industry compatible 45-nm model parameters, Monte Carlo HSPICE simulation results show that the conventional sensing circuit optimized using different types of transistors achieves read access pass yield enhancement of 10% when compared to the conventional sensing circuit using typical transistors.

  • Behavioral models for microwave circuit optimization

    Contemporary microwave circuit design is based on EM simulations and complex simulation models. Simulation model design is a must for growing number of devices and systems for which theoretical (e.g., analytical) models are either not available or not sufficiently accurate to yield the design satisfying given performance requirements. As prototype manufacture is very costly, the use of computer simulations has become commonplace as a feasible alternative for manufactures and also for education. Accurate numerical evaluations are computationally expensive; particularly for complex microwave/microstrip structures and computationally efficient EM-driven design optimization can be realized using physically based behavioral models.

  • Parametric Circuit Optimization with Reinforcement Learning

    In this paper, we focus on solving parametric optimization problems. Such kind of problems is very commonly seen in reality. We propose an efficient method to train a model that connects the solution to the parameters and thus solve all the problems with the same structure and different parameters at the same time. During the training process, instead of solving a series of optimization problems with randomly sampled w independently, we adopt reinforcement learning to accelerate the training process. Two networks are trained alternately. The first network is a value network, and it is trained to fit the target loss function. The second network is a policy network, whose output is connected to the input of the value network and it is trained to minimize the output of the value network. Experiments demonstrate the effectiveness of the proposed method.



Standards related to Circuit Optimization

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No standards are currently tagged "Circuit Optimization"