Conferences related to Wafer Technology

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2021 IEEE Photovoltaic Specialists Conference (PVSC)

Photovoltaic materials, devices, systems and related science and technology


2020 IEEE International Symposium on Antennas and Propagation and North American Radio Science Meeting

The joint meeting is intended to provide an international forum for the exchange of information on state of the art research in the area of antennas and propagation, electromagnetic engineering and radio science


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


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Periodicals related to Wafer Technology

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Advanced Packaging, IEEE Transactions on

The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.


Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Biomedical Engineering, IEEE Transactions on

Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.


Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems Magazine, IEEE


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Most published Xplore authors for Wafer Technology

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Xplore Articles related to Wafer Technology

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Next generation 650V CSTBT<sup>TM</sup> with improved SOA fabricated by an advanced thin wafer technology

2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2015

Using an advanced thin wafer technology, we have successfully fabricated the next generation 650V class IGBT with an improved SOA and maintaining the narrow distribution of the electrical characteristics for industrial applications. The applied techniques were the finer pattern transistor cell, the thin wafer process and the optimized back side doping concentration profiles. With the well organized back-side wafer process, ...


Design of tactile sensor using dynamic wafer technology based on VLSI technique

2001 Conference Proceedings of the 23rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2001

The study has been conducted with the objective of a real time control analysis with tactile sensors. This has led to the design and fabrication of a cost-effective artificial tactile sensor. The wafer technology is based on potentiometric principles. In the process, an in-depth study has been made keeping in view the reliability, accuracy, data processing, and flexibility. Very large ...


Micro-machined dielectrically isolated (MMDI) wafer technology [SOI]

1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199), 1998

This paper describes a new economical alternative to costly bonded silicon-on- insulator (BSOI) wafers in which dielectrically isolated wafers are fabricated from single bulk silicon wafers. Initial processing involves trench etching through a single wafer to a predefined depth using micro-machining tools. The trenches are filled with an insulator to provide lateral dielectric isolation. Standard semiconductor processing is performed. The ...


17.5um thin Cu wire bonding for fragile low-K wafer technology

2010 12th Electronics Packaging Technology Conference, 2010

This paper describes the challenges of a 17.5um thin bare Cu wire bonding on aluminum bond pads for a fragile low-k wafer technology, on a BGA package. Previous evaluations have so far focused on 20um and 25um bare Cu wires as a suitable low cost replacement for Au wires. To improve performance, more fragile low-k wafer technology is being developed. ...


The reverse blocking IGBT for matrix converter with ultra-thin wafer technology

ISPSD '03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings., 2003

An isolation type vertical 600V-50A IGBT with reverse blocking capability (RB- IGBT) has been developed for the first time. Ultra-thin wafer technology combined with deep boron diffusion technique results in a great improvement on trade-off performance. RB-IGBT can be used as a bi-directional switch by anti- parallel connection with another RB-IGBT. These bi-directional switches realize a high efficiency matrix converter.


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Educational Resources on Wafer Technology

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IEEE-USA E-Books

  • Next generation 650V CSTBT<sup>TM</sup> with improved SOA fabricated by an advanced thin wafer technology

    Using an advanced thin wafer technology, we have successfully fabricated the next generation 650V class IGBT with an improved SOA and maintaining the narrow distribution of the electrical characteristics for industrial applications. The applied techniques were the finer pattern transistor cell, the thin wafer process and the optimized back side doping concentration profiles. With the well organized back-side wafer process, the practically large chip has achieved without any sacrifice of the production yield. As a results, VCEsat-Eoff trade-off relationship and an Energy of Short Circuit by active Area (ESC/A) are improved in comparison with the conventional Punch Through (PT) structure.

  • Design of tactile sensor using dynamic wafer technology based on VLSI technique

    The study has been conducted with the objective of a real time control analysis with tactile sensors. This has led to the design and fabrication of a cost-effective artificial tactile sensor. The wafer technology is based on potentiometric principles. In the process, an in-depth study has been made keeping in view the reliability, accuracy, data processing, and flexibility. Very large scale integration (VLSI) computing array techniques have been incorporated to develop an independent logic control for real time analysis.

  • Micro-machined dielectrically isolated (MMDI) wafer technology [SOI]

    This paper describes a new economical alternative to costly bonded silicon-on- insulator (BSOI) wafers in which dielectrically isolated wafers are fabricated from single bulk silicon wafers. Initial processing involves trench etching through a single wafer to a predefined depth using micro-machining tools. The trenches are filled with an insulator to provide lateral dielectric isolation. Standard semiconductor processing is performed. The back side of the silicon is then removed to at least the level of the bottom of the trenches, and an insulating oxide is deposited on the back surface. We call this new technology micro-machined dielectric isolation (MMDI). This new technology reduces the cost of producing DI wafers by over 30% compared to BSOI technology, due to the reduction in the materials and the processing steps. Opto-electronic devices have been fabricated using MMDI technology with yields, performance, and reliability comparable to devices fabricated using the standard BSOI production process.

  • 17.5um thin Cu wire bonding for fragile low-K wafer technology

    This paper describes the challenges of a 17.5um thin bare Cu wire bonding on aluminum bond pads for a fragile low-k wafer technology, on a BGA package. Previous evaluations have so far focused on 20um and 25um bare Cu wires as a suitable low cost replacement for Au wires. To improve performance, more fragile low-k wafer technology is being developed. In the past, some key technical challenges experienced are the substantial aluminum splash and potential cracks underneath the bond pads. This paper will focus on using a thin Cu wire of 17.5um diameter to address the smaller BPO of 44um, with very minimal aluminum splash, and prevent any cracks on a fragile low-k construction. As copper is a harder material than aluminum, to make a good bonding interconnect between the two metals and yet addressing these concerns, is critical. Also, the bonded ball bond should have a sufficient amount of remnant aluminum to survive reliability test. As Cu oxidation is rampant, an inert environment of a forming gas of 95N<sub>2</sub>5H<sub>2</sub> is needed to contain this aspect in order to achieve a good wire bond. To address the small BPO and with the aluminum splash which will pose the likelihood of shorting between adjacent ball bonds, a small bonded ball bond size is important. Process parameter optimization coupled with wire bonder hardware and software capabilities are crucial. Acknowledging these concerns, the selection of the capillary was given much thought. Such a capillary must achieve the small bonded ball bond desired, and in association with process optimization, minimize the aluminum splash, ensure remnant aluminum, and finally to address any potential damage to the fragile lowk construction underneath the bond pads. The prescribed approach would be to use a lower set of bond process parameters. Hence, the selected capillary design must be able to achieve such criteria. Evaluations on a wire bonder equipped with a Cu kit, using a 17.5um thin bare Cu wire together with a special low-k capillary design, and with a bonding temperature of 150 deg C, showed promising initial data. At time zero, all traditional wire bond process buy-off criteria are met. However, some lifted ball bonds were observed during the wire pull, with the readings greater than 2gf criteria. Further optimization and refinement is needed. Of course, the necessary reliability test data must follow suit. Also, cross-sectional analysis did not reveal any damage or cracks to the fragile low-k regions below the bond pads. Cu wire to aluminum bond pad interface creates an intermetallics phase that is prone to corrosion after certain stress test conditions. Some studies have shown that the addition of Pd, or Palladium, can overcome this corrosion. With this in mind, the evaluations also include using a Pd coated Cu wire of similar size. Like the bare Cu wire, time zero data showed viability for the Pd coated wire as well. In fact, initial data showed an improvement over the bare Cu wire for standard wire bond process buy-off criteria. The above evaluations have demonstrated that a 17.5um thin bare Cu as well as Pd coated thin Cu wires showed somewhat similar positive initial results on a low-k wafer. Of course there are still many technical challenges as well as reliability considerations to overcome, before the proliferation of 17.5um Cu wire on such a fragile wafer technology.

  • The reverse blocking IGBT for matrix converter with ultra-thin wafer technology

    An isolation type vertical 600V-50A IGBT with reverse blocking capability (RB- IGBT) has been developed for the first time. Ultra-thin wafer technology combined with deep boron diffusion technique results in a great improvement on trade-off performance. RB-IGBT can be used as a bi-directional switch by anti- parallel connection with another RB-IGBT. These bi-directional switches realize a high efficiency matrix converter.

  • 600V LPT-CSTBT™ on advanced thin wafer technology

    Electrical characteristics of the fabricated 600V class CSTBT™ with a Light Punch Through (LPT) structure on an advanced thin wafer technology are presented for the first time. The electrical characteristics of LPT-CSTBT are superior to the conventional Punch Through type (PT) one, especially in low current density regions because of the inherent lower built-in potential. Furthermore, we also have evaluated the effects of the mechanical stress on the device characteristics after soldering, utilizing a novel evaluation method with a very small size sub-chip layout. The results validate the proposed tool is useful to examine the influence of the mechanical stress on the electrical characteristics.

  • Laser backside contact annealing of SiC power devices: A prerequisite for SiC thin wafer technology

    We developed a new backside contact formation process for SiC power devices based on pulsed laser annealing providing an ohmic contact with lower contact resistance and better adhesion properties than contacts formed by conventional rapid thermal annealing. This process does not add any significant thermal budget to the wafer front side and therefore allows a “short thin wafer” process, means completing the wafer front side including the imide process before thinning and backside metallization. By that means both the risk of wafer breakage and substrate contribution to the total device resistance are minimized at the same time. This is clearly shown by comparing 650V SiC Schottky diodes with identical device structure but different total chip thickness (360 vs 110 μm). Besides the advantage in differential resistance also other properties like heat flux through the device (Rth), non destructive surge current density (I2t) and reliability are improved by the SiC thin wafer technology enabled by the laser backside contact annealing.

  • Resonant pressure sensor with through-glass electrical interconnect based on SOI wafer technology

    This paper presents a resonant pressure sensor based on SOI wafer technology. In this device, pressure under measurement causes a deflection of a pressure- sensitive silicon square diaphragm, which is further translated to stress build up in “H” type doubly-clamped micro resonant beams, leading to resonant frequency shift. In device fabrication, through-glass vias and silicon-to- glass anodic bonding technologies were utilized. A high-strength hermetic sealing was then achieved after anodic bonding, with the resonators working in vacuum. Experimental results recorded a device resolution of 10pa, with the nonlinearity of 0.03% when pressure varying from 10kPa to 100kPa.

  • Development of Planar Microcoils for an Electromagnetic Linear Actuator Fabricated in Batch-Type Wafer Technology

    This paper presents the characterization of planar microfabricated coils designed for an electromagnetic system which is realized in batch-type wafer technology. The challenge is to fabricate good coils in the simplest and economic way. The process flow used for their fabrication in the clean room as well as the manufacture results are discussed. After the magnetic simulations and the electric characterization, the thermal behaviour of the microfabricated coils is observed to determine the maximal allowed current density and the corresponding heating. These are the main characteristics to know for the sizing of an electromagnetic system.

  • Top-Gate Molding Process Development of Cavity Down TBGA for High Density Wire Bonding and Low K Dielectric Wafer Technology Application

    Top-gate molding systems have been commercially available for mass production for more than 5 years. Key attractions to this relatively new molding concept are its improvement in wire sweep performance for ultra fine pitch wire bonding and ability to capitalize desirable mold compound mechanical properties over liquid encapsulation material for low k dielectric wafer technology application. This paper covers the development effort of top-gate molding in Freescale Semiconductor to replace liquid encapsulation process for cavity down TBGA package. Besides the ultra fine pitch and multi-tiers wire bonding, the key challenges of the development include substrate level delamination at various layers. Molding process conditions, substrate design, and mismatch between substrate and molding compound properties were identified as the causes of delamination. Design of experiments and finite element analysis (FEA) simulation methodologies were applied to determine the optimum molding process conditions and the suitable substrate base material properties for overall process robustness improvement. With the robust design in place, package performance and reliability at MSL3@260C and 1000 cycles temperature cycling has been successfully achieved.



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