Conferences related to Baseband Architectures

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2020 IEEE International Symposium on Antennas and Propagation and North American Radio Science Meeting

The joint meeting is intended to provide an international forum for the exchange of information on state of the art research in the area of antennas and propagation, electromagnetic engineering and radio science


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


2020 IEEE Radio and Wireless Symposium (RWS)

RWW2020 will be an international conference covering all aspects of radio and wireless. RWW2020's multidisciplinary events will bring together innovations that are happening across the broad wireless spectrum. RWS2020, this conference application, acts as the main conference for the entire RWW of events that includes the following conferences: PAWR2020, SiRF2020, WiSNet2020, and TWiOS2020 (IEEE Topical Conference on RF/microwave Power Amplifiers, IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, IEEE Topical Conference on Wireless Sensors and Sensor Networks, and IEEE Topical Workshop on the Internet of Space IoS, respectively). In addition to traditional podium presentations and poster sessions, tracks for IEEE Distinguished Lectures, Sunday half-day workshops, Monday panels, and a demo session are planned. A RWW2020 plenary talk are a parallel IoT Summit are planned. A student competition is also planned.

  • 2019 IEEE Radio and Wireless Symposium (RWS)

    This is a conference with a focus on wireless components, applications, and systems that impact both our current and future life style. The conference's main niche is to bring together technologists, circuit designers, system designers, and entrepreneurs at a single event. It was and is the place where these worlds meet, where new processes and systems can be benchmarked against the needs of circuit designers at the bleeding edge of RF systems, where today's design compromises can trigger tomorrow's advanced technologies. Where dreams can become a reality. RWS is the cornerstone conference for Radio Wireless Week.

  • 2018 IEEE Radio and Wireless Symposium (RWS)

    This is a set of five conferences with a focus on wireless components, applications, and systems that effect both now and our future life style. These conferences main niche is to bring together technologists, circuit designers, system designers, and entrepreneurs at a single event. It was and is the place where these worlds meet, where new processes and systems can be benchmarked against the needs of circuit designers at the bleeding edge of RF systems, where today’s design compromises can trigger tomorrow’s advanced technologies. Where dreams can become a reality.

  • 2017 IEEE Radio and Wireless Symposium (RWS)

    This is a set of five conferences with a focus on wireless components, applications, and systems that effect both now and our future life style. These conferences main niche is to bring together technologists, circuit designers, system designers, and entrepreneurs at a single event. It was and is the place where these worlds meet, where new processes and systems can be benchmarked against the needs of circuit designers at the bleeding edge of RF systems, where today’s design compromises can trigger tomorrow’s advanced technologies. Where dreams can become a reality.

  • 2016 IEEE Radio and Wireless Symposium (RWS)

    This is a set of five conferences with a focus on wireless components, applications, and systems that effect both now and our future life style. These conferences main niche is to bring together technologists, circuit designers, system designers, and entrepreneurs at a single event. It was and is the place where these worlds meet, where new processes and systems can be bench-marked against the needs of circuit designers at the bleeding edge of RF systems, where today

  • 2015 IEEE Radio and Wireless Symposium (RWS)

    This is a set of five conferences with a focus on wireless components, applications, and systems that effect both now and our future life style. These conferences main niche is to bring together technologists, circuit designers, system designers, and entrepreneurs at a single event. It was and is the place where these worlds meet, where new processes and systems can be benchmarked against the needs of circuit designers at the bleeding edge of RF systems, where today

  • 2014 IEEE Radio and Wireless Symposium (RWS)

    RWS focuses on the intersection between radio systems and wireless technology, which creates a unique forum for engineers to discuss hardware design and system performance of the state -of-the-art wireless systems. Includes an expanded program on the latest information on wireless communications and networking, and associated enabling technologies as new services and applications emerge.

  • 2013 IEEE Radio and Wireless Symposium (RWS)

    RWS focuses on the intersection between radio systems and wireless technology, which creates a unique forum for engineers to discuss hardware design and system performance of the state-of-the-art wireless systems. Includes an expanded program on the latest information on wireless communications and networking, and associated enabling technologies as new services and applications emerge.

  • 2012 IEEE Radio and Wireless Symposium (RWS)

    RWS focuses on the intersection between radio systems and wireless technology, which creates a unique forum for engineers to discuss hardware design and system performance of the state-of-the-art wireless systems. Includes an expanded program on the latest information on wireless communications and networking, and associated enabling technologies as new services and applications emerge.

  • 2011 IEEE Radio and Wireless Symposium (RWS)

    All aspects of components and systems related to radio and wireless networks.

  • 2010 IEEE Radio and Wireless Symposium (RWS)

    RWS focuses on the intersection between radio systems and wireless technology, which creates a unique forum for engineers to discuss various aspects of wireless communication systems and the state-of-the-art in both fields by exploring the connections between hardware design and system performance.

  • 2009 IEEE Radio and Wireless Symposium (RWS)

    This symposium highlights the state of the art of hardware and systems of radio and wireless

  • 2008 IEEE Radio and Wireless Symposium (RWS)

  • 2007 IEEE Radio and Wireless Symposium (RWS)

  • 2006 IEEE Radio and Wireless Symposium (RWS)

  • 2004 IEEE Radio and Wireless Conference - (RAWCON 2004)

  • 2003 IEEE Radio and Wireless Conference - (RAWCON 2003)

  • 2002 IEEE Radio and Wireless Conference - (RAWCON 2002)

  • 2001 IEEE Radio and Wireless Conference - (RAWCON 2001)

  • 2000 IEEE Radio and Wireless Conference - (RAWCON 2000)

  • 1999 IEEE Radio and Wireless Conference - (RAWCON '99)

  • 1998 IEEE Radio and Wireless Conference - (RAWCON '98)


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Periodicals related to Baseband Architectures

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Aerospace and Electronic Systems Magazine, IEEE

The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Broadcasting, IEEE Transactions on

Broadcast technology, including devices, equipment, techniques, and systems related to broadcast technology, including the production, distribution, transmission, and propagation aspects.


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


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Most published Xplore authors for Baseband Architectures

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Xplore Articles related to Baseband Architectures

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Selective Spanning with Fast Enumeration: A Near Maximum-Likelihood MIMO Detector Designed for Parallel Programmable Baseband Architectures

2008 IEEE International Conference on Communications, 2008

ML and near-ML MIMO detectors have attracted a lot of interest in recent years. However, almost all of the reported implementations are delivered in ASIC or FPGA. Our contribution is to co-optimize the near-ML MIMO detector algorithm and implementation for parallel programmable base-band architectures, such as DSPs with VLIW, SIMD or vector processing features. Although for hardware the architecture can ...


Joint Cell Assignment and Scheduling for Centralized Baseband Architectures

2015 IEEE 81st Vehicular Technology Conference (VTC Spring), 2015

This study considers a downlink cell association and scheduling mechanism for an LTE-Advanced network with a centralized architecture, featuring a central baseband (BB) pool and distributed small cells at the remote site. In the proposed solution, the BB pool determines the user-cell association to increase the network performance. A simple suboptimal algorithm with reduced complexity is used on a per ...


Hybrid lattice reduction algorithm and its implementation on an SDR baseband processor for LTE

2011 19th European Signal Processing Conference, 2011

Lattice Reduction (LR) is a promising technique to improve the performance of linear MIMO detectors. This paper proposes a Hybrid LR algorithm (HLR), which is a scalable LR algorithm. HLR is specifically designed and optimised to exploit ILP and DLP features offered by parallel programmable baseband architectures. Abundant vector-parallelism in HLR is enabled with highly- regular and deterministic data-flow. Hence, ...


Flexible Baseband Architectures for Future Wireless Systems

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008

The mobile communication systems today, have different radio spectrum, radio access technologies, and protocol stacks depending on the network being utilized. This gives rise to need of a flexible hardware platform that is capable of supporting all the different standards in the entire wireless communication frequency range. We present a generic baseband prototype architecture for SDR applications, subdivided into a ...


Model for energy optimization of baseband architectures in wireless communications

2012 International ITG Workshop on Smart Antennas (WSA), 2012

Mobile communication needs battery energy. There is always a trade-off between power consumption and bit-error performance. To investigate this, power modeling of the hardware components is necessary. In this paper, a baseband energy model for VLSI design optimization considering both dynamic and static energy consumption for wireless application with short distance is introduced. Due to the trade-off between dynamic and ...


More Xplore Articles

Educational Resources on Baseband Architectures

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IEEE.tv Videos

Gigabit Baseband Modem Technology for 5G millimetre wave applications - Mark Barrett: Brooklyn 5G Summit 2017
IMS 2014 Enabling Technologies and Architectures for 5G Wireless
An 8-10GHz Upconversion Mixer, with a Low-Frequency Calibration Loop Resulting in Better Than -73dBc In-Band Spurs: RFIC Interactive Forum
Co-design of Power Amplifier and Dynamic Power Supplies for Radar and Communications Transmitters
Enhancing 5G+ Performance: ML & DL for 5G - Tim O'Shea - B5GS 2019
An FTNC Receiver with +32.5dBm Effective OB-IIP3 Using Baseband IM3 Cancellation: RFIC Interactive Forum 2017
5G Virtual RAN Network Architectures - Olufemi Adeyemi - IEEE Sarnoff Symposium, 2019
Open Systems Architecture for RF and Microwave Technologies: MicroApps 2015 - Mercury Systems
A Comparator Design Targeted Towards Neural Net - David Mountain - ICRC San Mateo, 2019
The EU Human Brain Project - A Systematic Path from Data to Synthesis
A 4mW-RX 7mW-TX IEEE 802.11ah Fully-Integrated RF Transceiver: RFIC Industry Showcase 2017
Abstraction and Modeling of Cyber Security tutorial, Part 1
Coherent Photonic Architectures: The Missing Link? - Hideo Mabuchi: 2016 International Conference on Rebooting Computing
Dissecting Design Choices in Continuous-time Delta-Sigma Converters
Micro-Apps 2013: Alternative Methods and Optimization Techniques for Vector Modulation
The Future of Work on a Robot Economy
European Parliament Regulatory Efforts on Robotics
Prospects and Challenges for GHz to THz Technologies/Architectures for Future Wireless Communications pt.1
Cognitive RAN: Next Generation 6G Network - Parag Naik - India Mobile Congress, 2018
Abstraction and Modeling of Cyber Security tutorial, Part 2

IEEE-USA E-Books

  • Selective Spanning with Fast Enumeration: A Near Maximum-Likelihood MIMO Detector Designed for Parallel Programmable Baseband Architectures

    ML and near-ML MIMO detectors have attracted a lot of interest in recent years. However, almost all of the reported implementations are delivered in ASIC or FPGA. Our contribution is to co-optimize the near-ML MIMO detector algorithm and implementation for parallel programmable base-band architectures, such as DSPs with VLIW, SIMD or vector processing features. Although for hardware the architecture can be tuned to fit algorithms, for programmable platforms the algorithm must be elaborately designed to fit the given architecture, so that efficient resource-utilizations can be achieved. By thoroughly analyzing and exploiting the interaction between algorithms and architectures, we propose the SSFE (selective spanning with fast enumeration) as an architecture-friendly near-ML MIMO detector. The SSFE has a distributed and greedy algorithmic structure that brings a completely deterministic and regular dataflow. The SSFE has been evaluated for coded OFDM transmissions over 802.11n channels and 3GPP channels. Under the same performance constraints, the complexity of the SSFE is significantly lower than the K-Best, the most popular detector implemented in hardware. More importantly, SSFE can be easily parallelized and efficiently mapped on programmable baseband architectures. With TI TMS320C6416, the SSFE delivers 37.4 - 125.3 Mbps throughput for 4x4 64 QAM transmissions. To the best of our knowledge, this is the first reported near-ML MIMO detector explicitly designed for parallel programmable architectures and demonstrated on a real-life platform.

  • Joint Cell Assignment and Scheduling for Centralized Baseband Architectures

    This study considers a downlink cell association and scheduling mechanism for an LTE-Advanced network with a centralized architecture, featuring a central baseband (BB) pool and distributed small cells at the remote site. In the proposed solution, the BB pool determines the user-cell association to increase the network performance. A simple suboptimal algorithm with reduced complexity is used on a per time instant basis. The challenges associated to the user measurement reports and the interference variablity are discussed. Compared to the usual case where users connect to the cell providing the highest received power and scheduling is performed independently within the cells, the proposed algorithm can provide up to a 70% median data rate gain.

  • Hybrid lattice reduction algorithm and its implementation on an SDR baseband processor for LTE

    Lattice Reduction (LR) is a promising technique to improve the performance of linear MIMO detectors. This paper proposes a Hybrid LR algorithm (HLR), which is a scalable LR algorithm. HLR is specifically designed and optimised to exploit ILP and DLP features offered by parallel programmable baseband architectures. Abundant vector-parallelism in HLR is enabled with highly- regular and deterministic data-flow. Hence, HLR can be easily parallelized and efficiently mapped on Software Defined Radio (SDR) baseband architectures. HLR can be adapted to operate in two different modes to achieve the best performance/cycle trade-off, which is highly desirable for SDR baseband processing. The proposed algorithm has been evaluated in the context of 3GPP- LTE and implemented on ADRES which is a Coarse Grain Reconfigurable Array (CGRA) processor. Most of the previously reported implementations of LR algorithms are for ASIC or FPGA. However, to the best of author's knowledge, this is the first reported LR algorithm explicitly designed and optimized, to have a scalable and adaptive implementation for a CGRA processor like ADRES. The reported implementation of HLR can achieve gains of up to 12 dB compared to ZF for MIMO detection.

  • Flexible Baseband Architectures for Future Wireless Systems

    The mobile communication systems today, have different radio spectrum, radio access technologies, and protocol stacks depending on the network being utilized. This gives rise to need of a flexible hardware platform that is capable of supporting all the different standards in the entire wireless communication frequency range. We present a generic baseband prototype architecture for SDR applications, subdivided into a high level control module and a digital signal processing engine. The DSP engine is composition of highly configurable processing blocks, each dedicated to specific algorithms based on the analysis of different standards. We also present the internal architecture, simulation results and use cases for different air-interfaces of two processing blocks as case studies.

  • Model for energy optimization of baseband architectures in wireless communications

    Mobile communication needs battery energy. There is always a trade-off between power consumption and bit-error performance. To investigate this, power modeling of the hardware components is necessary. In this paper, a baseband energy model for VLSI design optimization considering both dynamic and static energy consumption for wireless application with short distance is introduced. Due to the trade-off between dynamic and static energy consumption of CMOS gates, a new design rule for energy aware implementation is presented. As an example, the hardware design of an FFT block is analyzed. Over 70% of the energy is saved after the optimization using the presented energy model.

  • Scalable Block-Based Parallel Lattice Reduction Algorithm for an SDR Baseband Processor

    Lattice Reduction (LR) is a promising technique to improve the performance of linear MIMO detectors. In this paper the Scalable Block-based Parallel LR algorithm (SBP-LR) is proposed and optimized for parallel programmable baseband architectures offering ILP and DLP features. In our algorithm, architecture-friendliness is explicitly introduced from the very beginning of the algorithm/architecture co-design flow. In this context, abundant vector- parallelism is enabled with highly-regular and deterministic data-flow. Hence, SBP-LR can be easily parallelized and efficiently mapped on Software Defined Radio (SDR) baseband architectures. The proposed algorithm has been implemented on ADRES and is evaluated in the context of 3GPP LTE. Most of the previously reported algorithms are implemented for ASIC or FPGA. However, to the best of author's knowledge, this is the first reported LR algorithm explicitly optimized for a Coarse Grain Reconfigurable Array (CGRA) processor like ADRES.

  • A unified instruction set programmable architecture for multi-standard advanced forward error correction

    The continuously increasing number of communication standards to be supported in nomadic devices combined with the fast ramping design cost in deep submicron technologies claim for highly reusable and flexible programmable solutions. Software defined radio (SDR) aims at providing such solutions in radio baseband architectures. Great advances were recently booked in handset- targeted SDR, covering most of the baseband processing with satisfactory performance and energy efficiency. However, as it typically depicts a magnitude higher computation load, forward error correction (FEC) has been excluded from the scope of high throughput SDR solutions and let to dedicated hardware accelerators. The currently growing number of advanced FEC options claims however for flexibility there too. This paper presents the first application-specific instruction programmable architecture addressing in a unified way the emerging turbo- and LPDC coding requirements of 3GPP-LTE, IEEE802.11n, IEEE802.16(e) and DVB-S2/T2. The proposal shows a throughput from 0.07 to 1.25 Mbps/MHz with efficiencies round 0.32 nJ/bit/iter in turbo mode and round 0.085 nJ/bit/iter in LDPC mode. The area is lower than the cumulated area of dedicated turbo and LDPC solution.

  • Adaptive SSFE Near-ML MIMO Detector with Dynamic Search Range and 80-103Mbps Flexible Implementation

    In this paper, we will present a near-ML (maximum likelihood) MIMO (multiple input multiple output) detector explicitly optimized for parallel programmable baseband architectures, such as DSPs (digital signal processors) with VLIW (very long instruction word), SIMD (single instruction multiple data) or vector processing features. First, we propose the SSFE (selective spanning with fast enumeration) algorithm as an architecture friendly near-ML MIMO detector. The SSFE has a distributed and greedy algorithmic structure that brings a completely deterministic and regular dataflow. This enables efficient parallelization on programmable architectures. More importantly, in order to exploit the abundant flexibility enabled by programmable architectures, we propose an efficient online algorithm to adaptively adjust the search range of the SSFE according to the numerical properties of MIMO channel matrixes. Such adaptiveness brings significant throughput improvements at negligible performance degradations. Specifically, on VLIW DSP TI TMS320C6416, such a dynamic adaptation brings 2.62 times to 28.6 times improvements (comparing to the static SSFE) for 1/2 turbo-coded 4 times 4 64 QAM transmissions over 3GPP suburban macro channels, delivering 80 - 103 Mbps average throughput.

  • Performance assessment of baseband algorithms for direct conversion tactical software defined receivers: I/Q imbalance correction, image rejection, DC removal, and channelization

    This paper addresses issues relating to software-defined receivers. Namely radio frequency (RF) to baseband architectures and the signal processing algorithms involved. Several direct conversion receiver architectures are introduced and analyzed for their performance. Issues relating to the quadrature imbalances and DC offset impairments are analyzed and detailed. To estimate and compensate for these impairments, several DSP algorithms are proposed and simulated for use with these receivers.

  • 1000BASE-T Gigabit Ethernet baseband DSP IC design

    The design of the Gigabit Ethernet baseband DSP IC is based on IEEE standard 802.3ab and focuses on signal processing in 1000BASE-T PHY layer. To achieve the target bit-error rate (BER) of less than 10/sup -10/, the receiver must conquer channel impairments including Inter-Symbol Interference (ISI), Echo, Near-End Cross Talk (NEXT), and Far-End Cross Talk (FEXT). We present low- power, low complexity, and high performance architectures of Echo Canceller, joint Decision Feedback Equalizer, and Trellis Decoder of the baseband DSP receiver in Gigabit Ethernet. The proposed baseband architectures are integrated, co-simulated with the analog front end, and implemented in 2.5 V-0.25 /spl mu/m CMOS standard cell design flow.