Conferences related to Backplane Transceivers

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2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE International Semiconductor Laser Conference (ISLC)

The ISLC is dedicated to the latest developments in semiconductor lasers, amplifiers and LEDs, including: Semiconductor Optical Amplifiers, Silicon compatible lasers, VCSELs, Photonic band-gap and microcavity lasers, Grating controlled lasers, Multi-segment and ring lasers, Quantum cascade and interband, Sub-wavelength scale nanolasers, Mid IR and THz sources, InP, GaAs and Sb materials, Quantum dot lasers, High power and high-brightness lasers, GaN and ZnSe based UV to visible LEDs, Communications lasers, Semiconductor integrated optoelectronics.

  • 2018 IEEE International Semiconductor Laser Conference (ISLC)

    The International Semiconductor Laser Conference has a long tradition as the leadinginternational conference where researchers and engineers from all over the world meet to shareand discuss the latest developments in semiconductor lasers, amplifiers and LEDs. The 25thInternational Semiconductor Laser Conference will be held in Kobe Japan from 12- 15September 2016. The conference will include both oral and poster sessions of contributed andinvited papers, as well as a plenary session comprising reviews on a number of important andtimely topics. A rump session will feature special topics of current interest for discussion in amore relaxed and open atmosphere. In addition, attendees will be able to participate inworkshops on current hot topics during the first day of the conference. Technical results on allaspects of semiconductor lasers, amplifiers, LEDs and integrated devices, from basic physics ofnew materials and structures to new and improved device concepts are covered.

  • 2016 International Semiconductor Laser Conference (ISLC)

    The International Semiconductor Laser Conference has a long tradition as the leading international conference where researchers and engineers from all over the world meet to share and discuss the latest developments in semiconductor lasers, amplifiers and LEDs. The 25th International Semiconductor Laser Conference will be held in Kobe Japan from 12- 15 September 2016. The conference will include both oral and poster sessions of contributed and invited papers, as well as a plenary session comprising reviews on a number of important and timely topics. A rump session will feature special topics of current interest for discussion in a more relaxed and open atmosphere. In addition, attendees will be able to participate in workshops on current hot topics during the first day of the conference. Technical results on all aspects of semiconductor lasers, amplifiers, LEDs and integrated devices, from basic physics of new materials and structures to new and improved device concepts are covered.

  • 2014 International Semiconductor Laser Conference (ISLC)

    The IEEE International Semiconductor Laser Conference (ISLC) has a long tradition as the leading international conference where researchers and engineers from all over the world meet to share and discuss the latest developments in semiconductor lasers, amplifiers and LEDs. The 24th IEEE International Semiconductor Laser Conference will be held at the Melia Palas Atenea Hotel on the seafront in Palma on the beautiful island of Mallorca in the Mediterranean from 7 - 10 September 2014. The conference will include both oral and poster sessions of contributed and invited papers, as well as a plenary session comprising reviews on a number of important and timely topics. A rump session will feature special topics of current interest for discussion in a more relaxed and open atmosphere. In addition, attendees will be able to participate in workshops on current hot topics during the first day of the conference. Technical results on all aspects of semiconductor lasers, amplifiers, LEDs and integ

  • 2012 IEEE 23rd International Semiconductor Laser Conference (ISLC)

    The IEEE International Semiconductor Laser Conference (ISLC) has a long tradition as the leading international conference where researchers and engineers from all over the world meet to share and discuss the most recent developments in semiconductor lasers, amplifiers and LEDs. The 23rd IEEE International Semiconductor Laser Conference will be held at the San Diego Mission Valley Marriott, San Diego, California from 7-10 October 2012.

  • 2010 IEEE 22nd International Semiconductor Laser Conference (ISLC)

    The 22 nd IEEE International Semiconductor Laser Conference will be held at Ana Hotel Kyoto in Kyoto, Japan on 26-30 September, 2010. This biannual meeting has a long tradition of being the primary forum for the dissemination of the most recent scientific and technical achievements in the field of semiconductor lasers and related technologies. The conference will include oral and poster sessions of contributed papers, an invited session comprising reviews in a number of topics of current importance, and a r

  • 2008 IEEE 21st International Semiconductor Laser Conference (ISLC)

  • 2006 IEEE 20th International Semiconductor Laser Conference (ISLC)

  • 2004 IEEE 19th International Semiconductor Laser Conference (ISLC)

  • 2002 IEEE 18th International Semiconductor Laser Conference (ISLC)

  • 2000 IEEE 17th International Semiconductor Laser Conference (ISLC)

  • 1996 IEEE 15th International Semiconductor Laser Conference (ISLC)


2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


2020 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI)

This symposium pertains to the field of electromagnetic compatibility.


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Periodicals related to Backplane Transceivers

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Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Communications Magazine, IEEE

IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...


Lightwave Technology, Journal of

All aspects of optical guided-wave science, technology, and engineering in the areas of fiber and cable technologies; active and passive guided-wave componentry (light sources, detectors, repeaters, switches, fiber sensors, etc.); integrated optics and optoelectronics; systems and subsystems; new applications; and unique field trials.


Micro, IEEE

IEEE Micro magazine presents high-quality technical articles from designers, systems integrators, and users discussing the design, performance, or application of microcomputer and microprocessor systems. Topics include architecture, components, subassemblies, operating systems, application software, communications, fault tolerance, instrumentation, control equipment, and peripherals.


Nuclear Science, IEEE Transactions on

All aspects of the theory and applications of nuclear science and engineering, including instrumentation for the detection and measurement of ionizing radiation; particle accelerators and their controls; nuclear medicine and its application; effects of radiation on materials, components, and systems; reactor instrumentation and controls; and measurement of radiation in space.


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Most published Xplore authors for Backplane Transceivers

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No authors for "Backplane Transceivers"


Xplore Articles related to Backplane Transceivers

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A 15mW 3.125GHz PLL for serial backplane transceivers in 0.13 /spl mu/m CMOS

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005., 2005

A 3.125GHz PLL fabricated in a 0.13 /spl mu/m CMOS process in a area of 0.064mm/sup 2/ is described. The PLL uses an architecture optimized for low noise, low power and small die area. In steady-state operation, the PLL forces the up and down currents in the charge pump to match one another. The total measured jitter is 1.3ps rms ...


A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers

IEEE Custom Integrated Circuits Conference 2006, 2006

We present a 5Gb/s transmitter that cancels the reflected signals from any impedance discontinuity located at up to 64UI away from the transmitter and spread over 8UI interval. Measured results from our 0.11mum CMOS design reveal a 150mV eye-opening, from a nearly closed eye, when reflection cancellation is activated. The design consumes 510muA for the PLL operation, 60mA for data ...


Decision-Feedback-Equalizer for 10-Gb/s backplane transceivers for highly lossy 56-inch channels

2008 International Conference on Communications, Circuits and Systems, 2008

This paper presents a decision-feedback-equalizer for 10-Gb/s backplane transceivers for highly lossy channels. Forward equalization is not used in order to avoid noise enhancement. The sampling phase is optimized to achieve maximum signal-to-noise-ratio at the sampling instants. The coefficients of feedback finite-impulse-response filter and the gain of variable-gain- amplifier are obtained automatically by adaptive circuits. The vertical eye opening is ...


Session 3 overview - backplane transceivers

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005., 2005

None


Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data

IEEE Journal of Solid-State Circuits, 2008

A full study of three data formats including duobinary, PAM4, and NRZ is proposed to estimate the performance of the corresponding transceivers under different conditions. Transceiver prototypes designed and optimized for the three signalings are presented to evaluate their performance as well as the feasibility. The three transceivers have been tested thoroughly in Rogers and FR4 boards. Fabricated in 90-nm ...


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Educational Resources on Backplane Transceivers

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IEEE-USA E-Books

  • A 15mW 3.125GHz PLL for serial backplane transceivers in 0.13 /spl mu/m CMOS

    A 3.125GHz PLL fabricated in a 0.13 /spl mu/m CMOS process in a area of 0.064mm/sup 2/ is described. The PLL uses an architecture optimized for low noise, low power and small die area. In steady-state operation, the PLL forces the up and down currents in the charge pump to match one another. The total measured jitter is 1.3ps rms when operating at 3.125GHz and the chip consumes 15mW.

  • A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers

    We present a 5Gb/s transmitter that cancels the reflected signals from any impedance discontinuity located at up to 64UI away from the transmitter and spread over 8UI interval. Measured results from our 0.11mum CMOS design reveal a 150mV eye-opening, from a nearly closed eye, when reflection cancellation is activated. The design consumes 510muA for the PLL operation, 60mA for data generation, and 50mA for data transmission, all from a 1.2V supply

  • Decision-Feedback-Equalizer for 10-Gb/s backplane transceivers for highly lossy 56-inch channels

    This paper presents a decision-feedback-equalizer for 10-Gb/s backplane transceivers for highly lossy channels. Forward equalization is not used in order to avoid noise enhancement. The sampling phase is optimized to achieve maximum signal-to-noise-ratio at the sampling instants. The coefficients of feedback finite-impulse-response filter and the gain of variable-gain- amplifier are obtained automatically by adaptive circuits. The vertical eye opening is almost doubled compared with a conventional decision-feedback- equalizer for a 56-inch channel with heavy loss more than -6.5 dB/GHz. The DFE is implemented in 0.13-mum IBM RF CMOS technologies. Results show an 8-tap DFE can open the highly blurred eye diagram, while a 12-tap conventional DFE can not open it. A 10-tap DFE yields a very clear eye diagram for PRBS-9 test patterns.

  • Session 3 overview - backplane transceivers

    None

  • Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data

    A full study of three data formats including duobinary, PAM4, and NRZ is proposed to estimate the performance of the corresponding transceivers under different conditions. Transceiver prototypes designed and optimized for the three signalings are presented to evaluate their performance as well as the feasibility. The three transceivers have been tested thoroughly in Rogers and FR4 boards. Fabricated in 90-nm CMOS technology, all three transceivers achieve error-free operation with 20-Gb/s 2 <sup>31</sup>-1 PRBS data over 40-cm Rogers and 10-cm FR4 channels. General comparison reveals that the NRZ data still achieves the best performance at 20 Gb/s.

  • Design techniques for CMOS backplane transceivers approaching 30-Gb/s data rates

    Serial link transceivers with sophisticated equalization are needed for data transmission over high-loss electrical channels such as backplanes. This paper highlights design techniques for extending the data rates of such circuits by describing a 28-Gb/s transceiver implemented in 32-nm SOI CMOS technology. Equalization is provided by a 4-tap feed-forward equalizer (FFE) in the transmitter and a two-stage peaking amplifier with active feedback topology and 15-tap decision-feedback equalizer (DFE) in the receiver. The transmitter employs a source-series terminated (SST) driver topology with double the speed of previous designs. The use of capacitive level-shifters allows a single current-integrating summer to drive the parallel paths used for speculating the first two DFE taps. Error-free signaling at 28 Gb/s is demonstrated over a 35-dB loss channel with a power consumption of 693 mW/lane.

  • A Simulator for High-Speed Backplane Transceivers

    A number of simulation methods dealing with measured S-parameters have been developed for the simulation of high-speed backplane transceivers and printed circuit board signal integrity analysis. Although these methods implemented in many circuit simulators provide correct system-level and transistor-level simulations, they usually fail to give correct results for many challenging backplane channels. This paper discusses a simulator that we developed which can give correct simulation results for those channels. It can also process those channel model files to allow commercial circuit simulators to give correct results.

  • 3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS

    The introduction of high-speed backplane transceivers inside FPGAs has addressed critical issues such as the ease in scalability of performance, high availability, flexible architectures, the use of standards, and rapid time to market. These have been crucial to address the ever-increasing demand for bandwidth in communication and storage systems [1-3], requiring novel techniques in receiver (RX) and clocking circuits.

  • Design of Energy-Efficient High-Speed Links via Forward Error Correction

    In this brief, we show that forward error correction (FEC) can reduce power in high-speed serial links. This is achieved by trading off the FEC coding gain with specifications on transmit swing, analog-to-digital converter (ADC) precision, jitter tolerance, receive amplification, and by enabling higher signal constellations. For a 20-in FR4 link carrying 10-Gb/s data, we demonstrate: 1) an 18-mW/Gb/s savings in the ADC; 2) a 1-mW/Gb/s reduction in transmit driver power; 3) up to 6× improvement in transmit jitter tolerance; and 4) a 25- to 40-mV improvement in comparator offset tolerance with 3× smaller swing.

  • High speed serial transceivers for data communication systems

    The architecture and critical circuit design issues for high-speed serial data links operating in excess of 1 Gb/s are described. Trade-offs in power vs. performance are presented for SONET/SDH transceivers and backplane transceivers for Infiniband or similar standards.



Standards related to Backplane Transceivers

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IEEE Standard for Electrical Characteristics of Backplane Transceiver Logic (BTL) Interface Circuits


IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI)

Specify a process-technology independent low voltage (less than 1V swing) to point to signal interface optimized for IEEE 1596 (SCI), using a defferential driver connected to a terminated receiver through a constant impedance transmission line.


IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI)

Specify a process-technology independent low voltage (less than 1V swing) to point to signal interface optimized for IEEE 1596 (SCI), using a defferential driver connected to a terminated receiver through a constant impedance transmission line.



Jobs related to Backplane Transceivers

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