Conferences related to Network-on-chip

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2019 21st International Conference on Advanced Communication Technology (ICACT)

With technically co-sponsored by IEEE ComSoc(Communications Society), IEEE ComSocCISTC(Communications & Information Security Technical Community), and IEEE ComSocONTC(Optical Networking Technical Community), the ICACT(International Conference onAdvanced Communications Technology) Conference has been providing an open forum forscholars, researchers, and engineers to the extensive exchange of information on newlyemerging technologies, standards, services, and applications in the area of the advancedcommunications technology. The conference official language is English. All the presentedpapers have been published in the Conference Proceedings, and posted on the ICACT Websiteand IEEE Xplore Digital Library since 2004. The honorable ICACT Out-Standing Paper Awardlist has been posted on the IEEE Xplore Digital Library also, and all the Out-Standing papersare subjected to the invited paper of the "ICACT Transactions on the Advanced Communications Technology" Journal issue by GIRI

  • 2018 20th International Conference on Advanced Communication Technology (ICACT)

    With technically co-sponsored by IEEE ComSoc(Communications Society), IEEE ComSoc CISTC(Communications & Information Security Technical Community), and IEEE ComSoc ONTC(Optical Networking Technical Community), the ICACT(International Conference on Advanced Communications Technology) Conference has been providing an open forum for scholars, researchers, and engineers to the extensive exchange of information on newly emerging technologies, standards, services, and applications in the area of the advanced communications technology. The conference official language is English. All the presented papers have been published in the Conference Proceedings, and posted on the ICACT Website and IEEE Xplore Digital Library since 2004. The honorable ICACT Out-Standing Paper Award list has been posted on the IEEE Xplore Digital Library also, and all the Out-Standing papers are subjected to the invited paper of the "ICACT Transactions on the Advanced Communications Technology" Journal issued by GIRI

  • 2017 19th International Conference on Advanced Communication Technology (ICACT)

    With technically co-sponsored by IEEE ComSoc(Communications Society), IEEE ComSoc CISTC(Communications & Information Security Technical Community), and IEEE ComSoc ONTC(Optical Networking Technical Community), the ICACT(International Conference on Advanced Communications Technology) Conference has been providing an open forum for scholars, researchers, and engineers to the extensive exchange of information on newly emerging technologies, standards, services, and applications in the area of the advanced communications technology. The conference official language is English. All the presented papers have been published in the Conference Proceedings, and posted on the ICACT Website and IEEE Xplore Digital Library since 2004. The honorable ICACT Out-Standing Paper Award list has been posted on the IEEE Xplore Digital Library also, and all the Out-Standing papers are subjected to the invited paper of the "ICACT Transactions on the Advanced Communications Technology" Journal issued by

  • 2016 18th International Conference on Advanced Communication Technology (ICACT)

    With technically co-sponsored by IEEE ComSoc(Communications Society), IEEE ComSoc CISTC(Communications & Information Security Technical Community), and IEEE ComSoc ONTC(Optical Networking Technical Community), the ICACT(International Conference on Advanced Communications Technology) Conference has been providing an open forum for scholars, researchers, and engineers to the extensive exchange of information on newly emerging technologies, standards, services, and applications in the area of the advanced communications technology. The conference official language is English. All the presented papers have been published in the Conference Proceedings, and posted on the ICACT Website and IEEE Xplore Digital Library since 2004. The honorable ICACT Out-Standing Paper Award list has been posted on the IEEE Xplore Digital Library also, and all the Out-Standing papers are subjected to the invited paper of the "ICACT Transactions on the Advanced Communications Technology" Journal issued by GiRI.

  • 2015 17th International Conference on Advanced Communication Technology (ICACT)

    With technically co-sponsored by IEEE ComSoc(Communications Society), IEEE ComSoc CISTC(Communications & Information Security Technical Community), and IEEE ComSoc ONTC(Optical Networking Technical Community), the ICACT(International Conference on Advanced Communications Technology) Conference has been providing an open forum for scholars, researchers, and engineers to the extensive exchange of information on newly emerging technologies, standards, services, and applications in the area of the advanced communications technology. The conference official language is English. All the presented papers have been published in the Conference Proceedings, and posted on the ICACT Website and IEEE Xplore Digital Library since 2004. The honorable ICACT Out-Standing Paper Award list has been posted on the IEEE Xplore Digital Library also, and all the Out-Standing papers are subjected to the invited paper of the "ICACT Transactions on the Advanced Communications Technology" Journal issued by GiRI.

  • 2014 16th International Conference on Advanced Communication Technology (ICACT)

    Technology, service, architecture, strategy, and policy in newly emerging system, standard, service, and variety of application on the area of telecommunications. ICACT 2014 provides an open forum for scholar, researcher, engineer, policy maker, network planner, and service provider in the advanced communication technologies.

  • 2013 15th International Conference on Advanced Communication Technology (ICACT)

    Technology, standard, service, architecture, strategy, and policy in newly emerging systems and a variety of applications in the area of communications. ICACT2013 provides an open forum for scholar, researcher, engineer, policy maker, network planner, and service provider in the advanced communications technologies.

  • 2012 14th International Conference on Advanced Communication Technology (ICACT)

    Technology, service, architecture, strategy, and policy in newly emerging systems, standards, service, and a variety of applications in the area of telecommunicatons. ICACT 2012 provides an open forum for scholars, researchers, engineers, policy makers, network planners, and service providers in the advanced communication technologies.

  • 2011 13th International Conference on Advanced Communication Technology (ICACT)

    International Conference on Advanced Communication Technology (ICACT) provides an open forum for researchers, engineers, policy, network planners, and service providers in the advanced communication technologies. Extensive exchange of information will be provided on newly emerging systems, standards, services, and variety of applications on the area of telecommunications.

  • 2010 12th International Conference on Advanced Communication Technology (ICACT)

    ICACT is an annual conference providing an open forum for researchers, engineers, network planners, and service providers in telecommunications. Extensive exchange of information will be provided on newly emerging systems, standards, services, and variety of applications in the area of telecommunications.

  • 2009 11th International Conference on Advanced Communication Technology (ICACT)

    ICACT is an annual conference providing an open forum for researchers, engineers, network planners, and service providers in telecommunications. Extensive exchange of information will be provided on newly emerging systems, standards, services, and variety of applications in the area of telecommunications.

  • 2008 10th International Conference Advanced Communication Technology (ICACT)

  • 2007 9th International Conference Advanced Communication Technology (ICACT)

  • 2006 8th International Conference Advanced Communication Technology (ICACT)

  • 2005 7th International Conference Advanced Communication Technology (ICACT)

  • 2004 6th International Conference Advanced Communication Technology (ICACT)


2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)

This conference is a forum for researchers and designers to present and discuss variousaspects of VLSI design, EDA, embedded systems, and enabling technologies. The program willconsist of regular paper sessions, special sessions, embedded tutorials, panel discussions,design contest, industrial exhibits and tutorials. This is the premier conference/exhibition in thisarea in India, attracting designers, EDA professionals, and EDA tool users. The programcommittee for the conference has a significant representation from the EDA researchcommunity and a large fraction of the papers published in this conference are EDA-related


2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE)

Electrical Engineering, Academic and Industrial


2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

This Symposium explores emerging trends and novel ideas and concepts in the area of VLSI. The Symposium covers a range of topics: from VLSI circuits, systems and design methods to system level design and system-on-chip issues, to bringing VLSI experience to new areas and technologies. Future design methodologies as well as new CAD tools to support them will also be the key topics. ISVLSI 2019 highlights a special theme of Neuromoprhic Computing. Over almost two decades the Symposium has been a unique forum promoting multidisciplinary research and new visionary approaches in the area of VLSI.

  • 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

    This Symposium explores emerging trends and novel ideas and concepts in the area of VLSI. The Symposium covers a range of topics: from VLSI circuits, systems and design methods to system level design and system-on-chip issues, to bringing VLSI experience to new areas and technologies. Future design methodologies as well as new CAD tools to support them will also be the key topics. ISVLSI 2018 highlights a special theme of Internet of Things. Over almost two decades the Symposium has been a unique forum promoting multidisciplinary research and new visionary approaches in the area of VLSI.

  • 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

    ISVLSI explores emerging trends and novel ideas and concepts in the area of VLSI. TheSymposium covers a range of topics: from VLSI circuits, systems and design methods tosystem level design and system-on-chip issues, to bringing VLSI experience to new areas andtechnologies like nano- and molecular devices, MEMS, and quantum computing. Future designmethodologies will also be one of the key topics at the workshop, as well as new CAD tools tosupport these technologies. Forthe past two decades, the conference has been a unique forum for promoting visionaryapproaches to VLSI design process and has been an esteemed venue for presentingmultidisciplinary research. The Symposium and researchers from academia and industry.

  • 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

    This Symposium explores emerging trends and novel ideas and concepts in the area of VLSI. The Symposium covers a range of topics: from VLSI circuits, systems and design methods to system level design and system-on-chip issues, to bringing VLSI experience to new areas and technologies. Future design methodologies as well as new CAD tools to support them will also be the key topics.

  • 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

    The scope of ISVLSI 2015 includes emerging trends and novel ideas and concepts in the area of VLSI. The ISVLSI 2015 will cover a range of topics: from VLSI circuits, systems and design methods to system-level design and system-on-chip issues, to bringing VLSI experience to new areas and technologies like nanotechnology device, molecular devices, MEMS, and quantum computing. ISVLSI 2015 will consider future design methodologies and new CAD tools to support them. Over almost two decades the symposium has been a unique forum promoting multidisciplinary research and new visionary approaches in the area of VLSI. The Symposium brings together leading scientists and researchers from academia and industry.

  • 2014 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

    ISVLSI explores emerging trends and novel ideas and concepts in the area of VLSI. The Symposium covers a range of topics: from VLSI circuits, systems and design methods to system level design and system-on-chip issues, to bringing VLSI experience to new areas and technologies like nano- and molecular devices, MEMS, and quantum computing. Future design methodologies will also be one of the key topics at the workshop, as well as new CAD tools to support these technologies. For the past two decades, the conference has been a unique forum for promoting visionary approaches to VLSI design process and has been an esteemed venue for presenting multidisciplinary research. The Symposium and researchers from academia and industry.

  • 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

    This Symposium explores emerging trends and novel ideas and concepts in the area of VLSI. The Symposium covers a range of topics: from VLSI circuits, systems and design methods to system level design and system-on-chip issues, to bringing VLSI experience to new areas and technologies like nano- and molecular devices, MEMS, and quantum computing. Future design methodologies will also be one of the key topics at the workshop, as well as new CAD tools to support them. Over almost two decades the symposium has been an unique forum promoting multidisciplinary research and new visionary approaches in the area of VLSI. The Symposium is bringing together leading scientists and researchers from academia and industry. The papers from this symposium have been published as the special issues of top archival journals. This fact indicates a very high quality of the symposium papers, and we are determined to keep a strong emphasis on this critical aspect of any conference.

  • 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

    ISVLSI explores emerging trends and novel ideas and concepts in the area of VLSI. The Symposium covers a range of topics: from VLSI circuits, systems and design methods to system level design and system-on-chip issues, to bringing VLSI experience to new areas and technologies like nano- and molecular devices, MEMS, and quantum computing.

  • 2011 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

    This Symposium explores emerging trends and novel ideas and concepts in the area of VLSI. The Symposium covers a range of topics: from VLSI circuits, systems and design methods to system level design and system-on-chip issues, to bringing VLSI experience to new areas and technologies like nano- and molecular devices, MEMS, and quantum computing.

  • 2010 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

    This Symposium explores emerging trends and novel ideas and concepts in the area of VLSI. The Symposium covers a range of topics: from VLSI circuits, systems and design methods to system level design and system-on-chip issues, to bringing VLSI experience to new areas and technologies like nano- and molecular devices, MEMS, and quantum computing. Future design methodologies will also be one of the key topics at the workshop, as well as new CAD tools to support them. Over almost two decades the symposium has

  • 2009 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

    This Symposium explores emerging trends and novel ideas and concepts in the area of VLSI. The Symposium covers a range of topics: from VLSI circuits, systems and design methods to system level design and system-on-chip issues, to bringing VLSI experience to new areas and technologies like nano- and molecular devices, MEMS, and quantum computing. Future design methodologies will also be one of the key topics at the workshop, as well as new CAD tools to support them.

  • 2008 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

    - Emerging Trends in VLSI, Nanoelectronics Molecular, Biological and Quantum - Computing, MEMS, VLSI Circuits and Systems, System Level Design, - Field-programmable & Reconfigurable Systems System-on-a-Chip Design, - Application-Specific Low Power VLSI System Design,System Issues in Complexity, - Low Power, Heat Dissipation, Power Awareness in VLSI Design Test and Verification, - Mixed-Signal Design and Analysis, Electrical/Packaging Co-Design, Physical Design, - Intellectual property creating and sha

  • 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

  • 2006 IEEE Annual Symposium on VLSI (ISVLSI)

  • 2005 IEEE Annual Symposium on VLSI (ISVLSI)

  • 2004 IEEE Annual Symposium on VLSI (ISVLSI)

  • 2003 IEEE Annual Symposium on VLSI (ISVLSI)

  • 2002 IEEE Workshop on VLSI (WVLSI)

  • 2001 IEEE Workshop on VLSI (WVLSI)

  • 2000 IEEE Workshop on VLSI (WVLSI)

  • 1999 IEEE Workshop on VLSI (WVLSI)

  • 1998 IEEE Workshop on VLSI

  • 1996 IEEE Workshop on VLSI


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Periodicals related to Network-on-chip

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Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Circuits and Systems Magazine, IEEE


Communications Magazine, IEEE

IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


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Most published Xplore authors for Network-on-chip

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Xplore Articles related to Network-on-chip

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Traffic Allocation: An efficient adaptive network-on-chip routing algorithm design

2016 2nd IEEE International Conference on Computer and Communications (ICCC), 2016

In recent years, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with higher communication requirements. Network-on-chip architectures emerged as promising solutions for future system-on-chip communication architecture designs. However, the switching and routing algorithm design of network-on- chip communication architectures are still facing great challenges. To address the deficiencies of the existing routing ...


Biomimicry to network on chip: Router heart rate

2015 27th International Conference on Microelectronics (ICM), 2015

The growing complexity of systems-on-chip creates the need to replace the bus- based architecture. Network-on-chip has been proposed to address the communication bottleneck of system-on-chip. Router is the key component of network-on-chip architecture. Router frequency is one of the critical parameters, which has direct impact on network-on-chip performance. This paper proposes an adaptive scheme for controlling the router frequency based ...


A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler

2014 IEEE COOL Chips XVII, 2014

A 36 Heterogeneous multicore processor is proposed to accelerate recognition- based markerless augmented reality. To enable a real-time operation of the proposed augmented reality, task-level pipelined multicore architecture with DLP/TLP optimized SIMD processing elements is implemented. In addition, the multicore employs a congestion-aware network-on-chip scheduler for 2D-mesh network-on-chip to support massive internal data transaction caused by task- level pipeline. As ...


A strategy for fault tolerant reconfigurable Network-on-Chip design

2016 20th International Symposium on VLSI Design and Test (VDAT), 2016

In this work we have proposed a fault tolerant reconfigurable Network-on-Chip (NoC) architecture that can endure router faults with graceful degradation in network performance. The routers which form the main building block of the interconnect network, have been modified to support multi-core connections. In case of router faults, the modified routers help to recover the healthy cores connected with the ...


A study of CSMA-based and token-based wireless interconnects network-on-chip

2014 IEEE International Conference on Communiction Problem-solving, 2014

The token passing multiple access (TPMA) scheme is a common adopted scheme for wireless network-on-chip (WiNoC) in chip multi-processors (CMPs). The drawback of TPMA is the channel access delay due to TPMA passing the token in a round- robin manner no matter the node has packets to send. In this paper, we study the performance of the slotted p-persistent carrier ...


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Educational Resources on Network-on-chip

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IEEE.tv Videos

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IEEE-USA E-Books

  • Traffic Allocation: An efficient adaptive network-on-chip routing algorithm design

    In recent years, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with higher communication requirements. Network-on-chip architectures emerged as promising solutions for future system-on-chip communication architecture designs. However, the switching and routing algorithm design of network-on- chip communication architectures are still facing great challenges. To address the deficiencies of the existing routing algorithms, a new adaptive network- on-chip routing algorithm: Traffic Allocation routing algorithm is proposed in this paper. The specifics of Traffic Allocation routing as well as the simulation results and analysis are also presented. For the proposed algorithm, traffic allocation registers are added to each of the routers to keep track of communication traffic loads for the four outgoing directions. Instead of monitoring the buffer depth of the neighboring routers, the proposed Traffic Allocation routing measures traffic loads based on local computation so as to reduce extra communication overhead. Simulation of the proposed Traffic Allocation routing algorithm and three existing routing algorithms has been carried out on NIRGAM network-on-chip simulator. Simulation results illustrate that the performance of the Traffic Allocation routing algorithm matches or exceeds the performance of the existing routing algorithms.

  • Biomimicry to network on chip: Router heart rate

    The growing complexity of systems-on-chip creates the need to replace the bus- based architecture. Network-on-chip has been proposed to address the communication bottleneck of system-on-chip. Router is the key component of network-on-chip architecture. Router frequency is one of the critical parameters, which has direct impact on network-on-chip performance. This paper proposes an adaptive scheme for controlling the router frequency based on biomimicry. A complete evaluation for the proposed scheme over various network-on-chip sizes and different evaluation parameters are performed. Results show improvement in throughput and latency. Moreover, it saves up to 75% of buffer storage, up to 60% of dynamic power and achieving load balance for all routers in the network.

  • A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler

    A 36 Heterogeneous multicore processor is proposed to accelerate recognition- based markerless augmented reality. To enable a real-time operation of the proposed augmented reality, task-level pipelined multicore architecture with DLP/TLP optimized SIMD processing elements is implemented. In addition, the multicore employs a congestion-aware network-on-chip scheduler for 2D-mesh network-on-chip to support massive internal data transaction caused by task- level pipeline. As a result, it achieves 1.22TOPS peak performance and 1.57TOPS/W energy-efficiency, which are 88% and 76% improvement over a state- of-the-art augmented reality processor, for 30fps 720p test input video.

  • A strategy for fault tolerant reconfigurable Network-on-Chip design

    In this work we have proposed a fault tolerant reconfigurable Network-on-Chip (NoC) architecture that can endure router faults with graceful degradation in network performance. The routers which form the main building block of the interconnect network, have been modified to support multi-core connections. In case of router faults, the modified routers help to recover the healthy cores connected with the faulty routers by dynamically reconfiguring itself and updating the routing table associated with individual routers.

  • A study of CSMA-based and token-based wireless interconnects network-on-chip

    The token passing multiple access (TPMA) scheme is a common adopted scheme for wireless network-on-chip (WiNoC) in chip multi-processors (CMPs). The drawback of TPMA is the channel access delay due to TPMA passing the token in a round- robin manner no matter the node has packets to send. In this paper, we study the performance of the slotted p-persistent carrier sense multiple access (CSMA) scheme on WiNoC. A comprehensive comparison of TPMA and CSMA is given in terms of throughput and access delay in this paper. Based on the study, we show that an appropriate p for the slotted CSMA can be obtained to achieve a high performance WiNoC for CMPs.

  • HM-Mesh: Energy Efficient Hybrid Multiple Network-on-Chip

    With the development of multiple processors SoC (system on chip), there are more and more challenges to the design of NoC (network-on-chip), one of which is to design energy-efficient NoC architecture, due to its large power consumption. Multi-NoC (multiple network-on-chip) has been proposed to save leakage power for its advantages in power gating network components. In this paper, we propose a hybrid Multi-NoC design, called HM-Mesh. HM-Mesh adopts a hybrid CMesh and Mesh architecture, and leverages CMesh network to respect its power efficiency at low network utilization. HMMesh is able to adaptively schedule packets to different subnets according to the network load, and smartly perform power gating to achieve good energy efficiency. The experimental results show that HMMesh delivers an average of 4.87% higher performance than Catnap, the state of the art power efficient Multi-NoC design. More importantly, HM-Mesh consumes an average of 29.2% less power than that of Catnap.

  • Efficient Router Architecture, Design and Performance Exploration for Many-Core Hybrid Photonic Network-on-Chip (2D-PHENIC)

    Nowadays, increasing emerging application complexity and improvement in process technology have enabled the design of many-core processors with tens to hundreds of cores on a single chip. Photonic Network-on-Chips (PNoCs) have recently been proposed as an alternative approach with high performance-per- watt characteristics for intra-chip communication. While providing large bandwidth through WDM (Wavelength Division Multiplexing), the main design challenge of conventional hybrid PNoC lies in the control layer, which is generally used for path set-up and also for short message communication. In this paper, we propose architecture and design of an efficient router for control and communication in heterogeneous Many-core Hybrid Photonic Network- on-Chip (2D-PHENIC). In addition, we present detailed complexity and performance evaluation of the proposed architecture.

  • Network-on-Chip Implementation of Midimew-Connected Mesh Network

    Architecture of interconnection network plays a significant role in the performance and energy consumption of Network-on-Chip (NoC) systems. In this paper we propose NoC implementation of Midi mew-connected Mesh Network (MMN). MMN is a Minimal Distance Mesh with Wrap-around (Midi mew) links network of multiple basic modules, in which the basic modules are 2D-mesh networks that are hierarchically interconnected for higher-level networks. For implementing all the links of level-3 MMN, minimum 4 layers are needed which is feasible with current and future VLSI technologies. With innovative combination of diagonal and hierarchical structure, MMN possesses several attractive features including constant node degree, small diameter, low cost, small average distance, and moderate bisection width than that of other conventional and hierarchical interconnection networks.

  • A configurable, programmable and software-defined network on chip

    The rapidly developing multi-cores integration on a chip requires efficient networking. To catch up the evolvement of on-chip network technologies and reduce the cost of redesign and redeployment, the software-defined solution is required on chip instead of proprietary design and straightforward replacement of hardware. In this paper, we propose the software defined on-chip network (SDNoC), which is a configurable and programmable network on chip with the idea of software defined networking. SDNoC separates on-chip network into the control plane and data forwarding plane, so that control logic is decoupled from the underlying chip hardware, and applications are able to configure the network according to their requirements. The simulation evaluates the SDNoC compared with the static and dynamic routing schemes in the traditional on- chip network, and shows SDNoC is able to improve the network performance and reduce power consumption with the programmable control logic and application- specific configuration.

  • ZigZag: An efficient deterministic Network-on-chip routing algorithm design

    As the technology scales toward deeper submicron, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with higher communication requirements. Network-on-chip architectures emerged as promising solutions for future system-on-chip communication architecture designs. However, the switching and routing algorithm design of network-on-chip communication architectures are still facing great challenges. To address the deficiencies of the existing routing algorithms, a new deterministic network-on-chip routing algorithm: ZigZag routing algorithm is proposed in this paper. The specifics of the algorithm as well as the simulation results and analysis are also presented. For the proposed ZigZag algorithm, the X direction and Y direction distances are compared. The packets are sent in the direction with the greater distance until they become equal at which point, the packets sent alternates between the X direction and the Y direction until they reach their destination. Simulation of the proposed ZigZag routing algorithm and two existing routing algorithms have been carried out on NIRGAM network-on-chip simulator. Simulation results illustrate that the performance of the ZigZag routing algorithm matches or exceeds the performance of the existing routing algorithms.



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