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The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.
2020 IEEE International Symposium on Circuits and Systems (ISCAS)
The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.
IBCAST is a scientific event covering wide range of topics in the fields of AdvancedMaterials,Aero Structures,Biomedical Sciences,Cyber Security & AssuranceTechnologies,Control and Signal Processing,Fluid Dynamics,Medical Sciences,UnderwaterTechnologies,Wireless Communication and Radar.
With technically co-sponsored by IEEE ComSoc(Communications Society), IEEE ComSocCISTC(Communications & Information Security Technical Community), and IEEE ComSocONTC(Optical Networking Technical Community), the ICACT(International Conference onAdvanced Communications Technology) Conference has been providing an open forum forscholars, researchers, and engineers to the extensive exchange of information on newlyemerging technologies, standards, services, and applications in the area of the advancedcommunications technology. The conference official language is English. All the presentedpapers have been published in the Conference Proceedings, and posted on the ICACT Websiteand IEEE Xplore Digital Library since 2004. The honorable ICACT Out-Standing Paper Awardlist has been posted on the IEEE Xplore Digital Library also, and all the Out-Standing papersare subjected to the invited paper of the "ICACT Transactions on the Advanced Communications Technology" Journal issue by GIRI
Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.
Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...
The design and manufacture of consumer electronics products, components, and related activities, particularly those used for entertainment, leisure, and educational purposes
2018 9th IEEE Control and System Graduate Research Colloquium (ICSGRC), 2018
Most existing works on application mapping for Multiprocessor System-on-Chip (MPSoC) use either simulation or analytical modeling to evaluate their mapping solutions. However, the use of these evaluation approaches is not as accurate as prototyping on a real MPSoC system. Rapid prototyping on a reconfigurable logic platform for design space exploration is also not trivial as tasks have to be developed ...
2018 IEEE Radiation Effects Data Workshop (REDW), 2018
This paper presents a test methodology using Xilinx System Validation Tool (SVT) design suite to characterize the single event response of Xilinx's 16nm Zynq Ultrascale+ MPSoC dual & quad ARM core processors. Accelerated SEU beam test of a XCZU9EG device was performed using the 64MeV Proton source at Crocker Nuclear Laboratory (CNL). Single-event characterization results are presented and categorized in ...
2010 International Conference on Anti-Counterfeiting, Security and Identification, 2010
With the improved performance of SoC for real-time application, more and more processing cores have been integrated into one chip, which is called MPSoC. One of the key problems is how to design the MPSoC architecture to improve the overall performance. In this paper, a cluster-based MPSoC using hierarchical on-chip communication is proposed. In the top level, on-chip network is ...
2010 International Conference on Anti-Counterfeiting, Security and Identification, 2010
Inter-Processor communication synchronization in multi-processor system-on- chip (MPSoC) is one of the key factors for the whole chip performance. It cannot only affect the efficiency of task-level parallelism, but also has high dependency on MPSoC hardware architecture. Two synchronization mechanisms, i.e. mailbox and packet switching, are studied and analyzed in Network on chip based MPSoC. At first, the two schemes ...
2017 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS), 2017
In a Multiprocessor System On Chip design (MPSOC), the Out-of-order (OoO) execution scheme makes a vital role in task-level parallelism circuit. Scheduling and mapping the tasks on the processing elements are the important challenges of OoO execution. At this level, the major drawback of current programming models is that programmers need to handle the task assignments manually, which would seriously ...
Most existing works on application mapping for Multiprocessor System-on-Chip (MPSoC) use either simulation or analytical modeling to evaluate their mapping solutions. However, the use of these evaluation approaches is not as accurate as prototyping on a real MPSoC system. Rapid prototyping on a reconfigurable logic platform for design space exploration is also not trivial as tasks have to be developed ground-up. This paper proposes a development environment for fast NoC-based MPSoC application prototyping. A conversion method called CAL2NoC is proposed to convert a high-level dataflow model of real-world applications to multiple executable C codes (tasks). These application tasks are executed on emulated Network-on-Chip (NoC) based MPSoC platform and run- time performance traces are collected. CAL2NoC facilitates prototype-based design space exploration for real-world applications using emulated MPSoC platform for practical performance evaluation. As a proof-of-concept, JPEG encoder is profiled using the proposed method. It has been shown that the proposed method facilitates a rapid development of emulated MPSoC for accurate application mapping evaluation.
This paper presents a test methodology using Xilinx System Validation Tool (SVT) design suite to characterize the single event response of Xilinx's 16nm Zynq Ultrascale+ MPSoC dual & quad ARM core processors. Accelerated SEU beam test of a XCZU9EG device was performed using the 64MeV Proton source at Crocker Nuclear Laboratory (CNL). Single-event characterization results are presented and categorized in terms of detectability and correctability. SEU test results show that the overall Processor System (PS) FIT FIT is ≤ 1, with all safety mechanisms enabled and no uncorrectable events were observed in the PS RAM.
With the improved performance of SoC for real-time application, more and more processing cores have been integrated into one chip, which is called MPSoC. One of the key problems is how to design the MPSoC architecture to improve the overall performance. In this paper, a cluster-based MPSoC using hierarchical on-chip communication is proposed. In the top level, on-chip network is used as the communication backbone for various clusters. In the cluster level, processing cores and IPs communicate with each others via a hierarchical bus. This paper focuses on the design and verification problems of computation cluster, which consists of several RISC processors and storage components. Separate control path and data path are designed to meet the performance requirements. The proposed architecture is implemented into a FPGA prototype. And a video application is mapped on the prototype to verify the functionality. Experiments show that the proposed MPSoC can work at 90 MHz and successfully accomplish real-time fade-in-fade-out processing of 4 lane videos which are 320*240 and 24 frames per second.
Inter-Processor communication synchronization in multi-processor system-on- chip (MPSoC) is one of the key factors for the whole chip performance. It cannot only affect the efficiency of task-level parallelism, but also has high dependency on MPSoC hardware architecture. Two synchronization mechanisms, i.e. mailbox and packet switching, are studied and analyzed in Network on chip based MPSoC. At first, the two schemes are implemented and verified in stand- alone mode, analyzed with communication latency, communication bandwidth and resource utilization. Furthermore, the two schemes are analyzed in MPSoC prototype environment that runs real-time fade-in fade-out video processing. Experimental results show that the mailbox based synchronization scheme has low latency and low resource overhead, but it is not feasible for large number of clusters due to the physical limitation. Although the packet based scheme has more latency, it has more scalability and feasibility.
In a Multiprocessor System On Chip design (MPSOC), the Out-of-order (OoO) execution scheme makes a vital role in task-level parallelism circuit. Scheduling and mapping the tasks on the processing elements are the important challenges of OoO execution. At this level, the major drawback of current programming models is that programmers need to handle the task assignments manually, which would seriously increase the burden of programmers. The Analysis of inter-task dependency is the main challenge for OoO in task level parallelism. Instruction level score boarding algorithm and Tomasulo algorithm are used in analysing inter-task dependences. The prototyped field programmable gate array (FPGA) fabric is composed of both software based static and dynamic implementation on top of a heterogeneous MPSOC. By combining the heterogeneous MPSOC with reconfigurable computing the computational capabilities of heterogeneous MPSOC will greatly improve. The trade-off between static and dynamic approaches can also be analysed. In this paper, modified score boarding algorithm is used along with particle swarm optimization technique. Particle swarm optimization improves the efficiency and performance.
With the development of semiconductor technology, more modules are integrated onto a single chip. Multiprocessor system-on-chip (MPSoC) is such circuit with multiple embedded processor cores on chip. It provides high parallelism with multi- threads through the multiple cores. Memory system is still the bottleneck of the performance and power-consumption of MPSoC systems. Scratchpad memory (SPM), which is software-controlled on-chip memory without extra tags, is used on MPSoC chips. SPM has low power-consumption and high efficiency compared to cache. However, the SPM requirements from different cores will be also different. How to balance the utilization of SPM is still a challenge. In this paper, we propose a new technique for SPM allocation on demand to reduce the power consumption and improve the performance of MPSoC. SPM will be shared under special constrains. Experimental results show that our approach can reduce both the execution time and the energy consumption effectively.
We have developed - and present in this article - a Master-Slave Multiprocessor System on Chip (MPSoC) for ECG analysis; it is based on Field Programmable Gate Array (FPGA). More exactly, it is a 3-processor MPSoC, where in principle, on one hand 2 slaves deal with some analysis of the signals of the 12-lead ECG standard and on another hand a master controls and coordinates the whole system. The Xilinx soft processor MicroBlaze is used as elementary processor and the 2 slaves communicate with the master by means 2 mailboxes via PLB bus. Due to the limited features of the available board at the time of experimentations, namely the Nexys 3 from Digilent featuring Xilinx SPARTAN 6 XC6SLX16 FPGA device, only a reduced software is tested, successfully, with the local memory of the used FPGA board. We have used different ECG signals from Physiobank databases for this qualitative evaluation of the proposed system. To our knowledge, this MPSoC implementation is novel, authentic and scalable.
MPSOC integrated a variety of heterogeneous components which require a communication between them. A solution to flexibility and reconfigurability of interconnects is the use of Network on Chip (NoC). These latter are likely proposing efficient solutions with the complex problems of the embedded system integrations. Multistage interconnection networks have been frequently proposed as connection means in classical multiprocessor systems. They are generally accepted concepts as on-chip communication platform. We describe in this paper the design methodology and the implementation of a Delta multistage interconnection network on chip. Also, we propose a flexible and an efficient model of MPSOC architecture based on Delta MIN. Finally, the effectiveness of the proposed design methodology is shown through parallelized applications on MPSoC architecture.
Wireless video interphone cannot only provide portability, but also connect people through video communication, so it gains more and more interest in consumer electronics. To design such systems, it needs high performance video processing engine. In this paper, a Multi-processor system on a chip (MPSoC) is designed, in which there are one 32-bit RISC CPU and a low power, high performance H.264 codec. The RISC CPU controls the system operation, and the H.264 codec is responsible for video decoding. Due to the large number of data to be processed, an off-chip DDRII SDRAM is used to store source stream and intermediate data. Additionally, the MPSoC can receive real-time wireless video and convert the decoded data into RGB data format that can be displayed on LCD. The MPSoC is implemented on EP3C120F780C8N FPGA, and takes up 71% resource of the total device resource. Experiment results show that it runs 32MHz, and can perform real-time video decoding, with the frame rate up to 30fps.
The buffer plays an important role in the design of MPSoC. The buffer mechanism influences the efficiency of link bandwidth. The buffer also provides a mechanism to synchronize the speed between the routers. The buffers are used to store packets or flits when they cannot be forwarded right away onto the output port. The paper presents discussion on buffering techniques used in the design of MPSoC. We have designed a synchronous Queue for 3-D MPSoC which could perform read and write operation at the same time. Firstly, we have designed a buffer using a multiplexer and a flip flop, and then we have proposed a buffer which would save at least 25% area of what we are using for mux based memory. It is designed using AND gated clock which also saves more power than any other design. We have generated full and AlmostFull signal to avoid overflow. The AlmostFull signal will be HIGH when only one location is EMPTY to write data. The AlmostFull and Full signals eliminate the overhead of sending credit information at every cycle. Thus, power dissipation from the buffers is reduced. The designed buffer using multiplexer operates at the maximum frequency of 755MHz and the proposed buffer has achieved a maximum frequency of 875 MHz on Vertex 6 device.
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Junior DSP/FPGA Programmer - EOSL
Georgia Tech Research Institute (GTRI)