Conferences related to Silicon On Insulator (SOI)

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2019 IEEE/MTT-S International Microwave Symposium - IMS 2019

Comprehensive symposium on microwave theory and techniques including active and passive circuit components, theory and microwave systems.

  • 2029 IEEE/MTT-S International Microwave Symposium - IMS 2029

    The IEEE International Microwave Symposium (IMS) is the world s foremost conference covering the UHF, RF, wireless, microwave, millimeter-wave, terahertz, and optical frequencies; encompassing everything from basic technologies to components to systems including the latest RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation and more. The IMS includes technical and interactive sessions, exhibits, student competitions, panels, workshops, tutorials, and networking events.

  • 2021 IEEE/MTT-S International Microwave Symposium - IMS 2021

    The IEEE MTT-S International Microwave Symposium (IMS) is the premier conference covering basic technologies, to passives and actives components to system over a wide range of frequencies including VHF, UHF, RF, microwave, millimeter-wave, terahertz, and optical. The conference will encompass the latest in RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation, wireless systems, RFID and related topics.

  • 2018 IEEE/MTT-S International Microwave Symposium - IMS 2018

    Microwave theory and techniques, RF/microwave/millimeter-wave/terahertz circuit design and fabrication technology, radio/wireless communication.

  • 2017 IEEE/MTT-S International Microwave Symposium - IMS 2017

    The IEEE MTT-S International Microwave Symposium (IMS) is the premier conference covering basic technologies, to passives and actives components to system over a wide range of frequencies including VHF, UHF, RF, microwave, millimeter-wave, terahertz, and optical. The conference will encompass the latest in RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation, wireless systems, RFID and related topics.

  • 2016 IEEE/MTT-S International Microwave Symposium - IMS 2016

    The IEEE International Microwave Symposium (IMS) is the world s foremost conference covering the UHF, RF, wireless, microwave, millimeter-wave, terahertz, and optical frequencies; encompassing everything from basic technologies to components to systems including the latest RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation and more. The IMS includes technical and interactive sessions, exhibits, student competitions, panels, workshops, tutorials, and networking events.

  • 2015 IEEE/MTT-S International Microwave Symposium - MTT 2015

    The IEEE MTT-S International Microwave Symposium (IMS) is the premier conference covering basic technologies, to passives and actives components to system over a wide range of frequencies including VHF, UHF, RF, microwave, millimeter-wave, terahertz, and optical. The conference will encompass the latest in RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation, wireless systems, RFID and related topics. The IMS includes technical sessions, both oral and interactive, worksh

  • 2014 IEEE/MTT-S International Microwave Symposium - MTT 2014

    IMS2014 will cover developments in microwave technology from nano devices to system applications. Technical paper sessions, interactive forums, plenary and panel sessions, workshops, short courses, industrial exhibits, and a wide array of other technical activities will be offered.

  • 2013 IEEE/MTT-S International Microwave Symposium - MTT 2013

    The IEEE MTT-S International Microwave Symposium (IMS) is the premier conference covering basic technologies, to passives and actives components to system over a wide range of frequencies including VHF, UHF, RF, microwave, millimeter -wave, terahertz, and optical. The conference will encompass the latest in RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation, wireless systems, RFID and related topics.The IMS includes technical and interactive sessions, exhibits, student competitions, panels, workshops, tutorials, and networking events.

  • 2012 IEEE/MTT-S International Microwave Symposium - MTT 2012

    The IEEE International Microwave Symposium (IMS) is the world s foremost conference covering the UHF, RF, wireless, microwave, millimeter-wave, terahertz, and optical frequencies; encompassing everything from basic technologies to components to systems including the latest RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation and more. The IMS includes technical and interactive sessions, exhibits, student competitions, panels, workshops, tutorials, and networking events.

  • 2011 IEEE/MTT-S International Microwave Symposium - MTT 2011

    The IEEE International Microwave Symposium (IMS) is the world s foremost conference covering the UHF, RF, wireless, microwave, millimeter-wave, terahertz, and optical frequencies; encompassing everything from basic technologies to components to systems including the latest RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation and more. The IMS includes technical and interactive sessions, exhibits, student competitions, panels, workshops, tutorials, and networking events.

  • 2010 IEEE/MTT-S International Microwave Symposium - MTT 2010

    Reports of research and development at the state-of-the-art of the theory and techniques related to the technology and applications of devices, components, circuits, modules and systems in the RF, microwave, millimeter-wave, submillimeter-wave and Terahertz ranges of the electromagnetic spectrum.

  • 2009 IEEE/MTT-S International Microwave Symposium - MTT 2009

    The IEEE International Microwave Symposium (IMS) is the world s foremost conference covering the UHF, RF, wireless, microwave, millimeter-wave, terahertz, and optical frequencies; encompassing everything from basic technologies to components to systems including the latest RFIC, MIC, MEMS and filter technologies, advances in CAD, modeling, EM simulation and more. The IMS includes technical and interactive sessions, exhibits, student competitions, panels, workshops, tutorials, and networking events.

  • 2008 IEEE/MTT-S International Microwave Symposium - MTT 2008

  • 2007 IEEE/MTT-S International Microwave Symposium - MTT 2007

  • 2006 IEEE/MTT-S International Microwave Symposium - MTT 2006


2015 IEEE International Reliability Physics Symposium (IRPS)

Sharing information related to cause, effects and solutions in the deign and manufacture of electronics and related components


2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD)

ISPSD is the premier forum for technical discussion in all areas of power semiconductor devices and power integrated circuits. Topics of interest include Device Physics, Device Design, Power Devices, Safe-Operating Area, Reliability, ESD, Process Integration, Modeling, Materials, Circuit Design, Power SoC, Packaging, Thermal Management.


2014 IEEE 45th Semiconductor Interface Specialists Conference (SISC)

The SISC provides a unique forum for device engineers, solid-state physicists, and materials scientists to discuss issues of common interest. Principal topics for discussion at SISC are semiconductor/insulator interfaces, the physics of insulating thin films, and the interaction among materials science, device physics, and state-of-the-art technology.


2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)

CSICS is a technology and integrated circuit conference showcasing many of the finest achievements made in compound semiconductor technology and circuits. CSICS has grown to encompass GaAs, InP, GaN, SiGe, SiC, InSb, nano-scale CMOS, and graphene semiconductor technologies and their application to RF, mm-wave, high-speed, and energy conversion circuits and systems. Specific technical areas of interest include: Innovative device concepts in emerging technologies, Nitrides, InP, III-V on Si, Ge on Si, Graphene, Analog, RF, mixed-signal, mm-wave, THz circuit blocks and ICs in III-V, CMOS, SiGe BiCMOS, Power conversion circuits and technologies, Optoelectronic and photonic devices and ICs, System applications, Wireless handsets and base stations, Vehicular and military RADAR, High-speed digital systems, Fiber optics and photonics, Device and circuit modeling / EM and EDA tools, Thermal simulation and advanced packaging of highpower devices and ICs, Device and IC manufacturing processes


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Periodicals related to Silicon On Insulator (SOI)

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Device and Materials Reliability, IEEE Transactions on

Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...


Microwave and Wireless Components Letters, IEEE

Published monthly with the purpose of providing fast publication of original and significant contributions relevant to all aspects of microwave/millimeter-wave technology. Emphasis is on devices, components, circuits, guided-wave structures, systems and applications covering the frequency spectrum from microwave and beyond, including submillimeter-waves and infrared.


Semiconductor Manufacturing, IEEE Transactions on

Addresses innovations of interest to the integrated circuit manufacturing researcher and professional. Includes advanced process control, equipment modeling and control, yield analysis and optimization, defect control, and manufacturability improvement. It also addresses factory modelling and simulation, production planning and scheduling, as well as environmental issues in semiconductor manufacturing.



Most published Xplore authors for Silicon On Insulator (SOI)

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Xplore Articles related to Silicon On Insulator (SOI)

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Plasma-activated bonding, controlled cleave process, and non-contact smoothing for Germanium-on-Insulator (GeOI) manufacturing

2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573), 2004

Transistor scaling limitations require profound changes in materials systems used to manufacture future generations of integrated circuits. Germanium-on- Insulator (GeOI) substrates have been proposed as one method to overcome the limitations of silicon and silicon on insulator substrates (SOI). GeOI substrates offer the advantages of the high electron and hole mobilities while at least partially overcoming the high leakage currents ...


Thin-film silicon-on-insulator (SOI) device applications of selective epitaxial growth

Proceedings of 1993 IEEE International SOI Conference, 1993

Silicon-on-insulator (SOI) technology has surged into a position of prominence in recent years. SOI devices provide a viable technology for high-density, large-scale-integration and high performance VLSI circuits. Of late, the potential applications of SOI devices have extended to the field of power devices and mixed-mode analog-digital circuits. In this field of application in particular, selective epitaxial growth techniques such as ...


An Embedded Silicon-Carbon S/D Stressor CMOS Integration on SOI with Enhanced Carbon Incorporation by Laser Spike Annealing

2007 IEEE International SOI Conference, 2007

We report a CMOS-compatible embedded silicon-carbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to 2.6% substitutional carbon (C<sub>sub</sub>) epitaxial Si:C and laser spike annealing (LSA) for increased C<sub>sub</sub> incorporation. 26% channel resistance (Rch) reduction and 11% Idlin-Ioff enhancement for 0.5% C<sub>sub</sub> and 60% Rch reduction for 2.2% C<sub>sub</sub> are demonstrated.


A guided tour of electronic design automation (EDA) for design of silicon on insulator (SOI) SoCs

2009 IEEE International SOI Conference, 2009

The design of SOI-based SoCs has traditionally been the province of a few companies that could afford very labor-intensive custom design approaches - microprocessor companies looking for performance or aerospace companies looking for rad-hard electronics. In recent years, SOI has become a more attractive option for SoC design teams that have traditionally targeted bulk silicon. With current improvements in SOI ...


Twin silicon nanowire FET (TSNWFET) On SOI with 8 nm silicon nanowires and 25 nm surrounding TiN gate

2008 IEEE International SOI Conference, 2008

In this work, fabrication of TSNWFET on SOI with down to 25-nm TiN surrounding gate and 8-nm silicon nanowires is reported with high manufacturability and improved device reliability including reduced junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. And high performance is also obtained to be 1124muA/mum and 1468muA/mum ...


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Educational Resources on Silicon On Insulator (SOI)

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IEEE.tv Videos

RF-pFET in Fully Depleted SOI Demonstrates 420GHz FT: RFIC Industry Showcase 2017
Electrically-Pumped 1.31 μm MQW Lasers by Direct Epitaxy on Wafer-Bonded InP-on-SOI Substrate - Yingtao Hu - Closing Ceremony, IPC 2018
Millimeter-Wave Bandpass Filter Using High-Q Conical Inductors and MOM Capacitors: RFIC Interactive Forum
Silicon Labs' Thunderboard Sense (SLTB001A): Mouser Engineering Bench Talk
Design of Monolithic Silicon-Based Envelope-Tracking Power Amplifiers for Broadband Wireless Applications
IMS MicroApps: Silicon Technology Solutions for Wireless Front End Modules
Silicon THz: an Opportunity for Innovation
High Efficiency SHG in Heterogeneously Integrated GaAs Ring Resonators - Lin Chang - Closing Ceremony, IPC 2018
Nanotechnology, we are already there: APEC 2013 KeyTalk with Dr. Terry Lowe
An IEEE IPC Special Session with Alexander Spott of The Optoelectronics Research Group
Single Crystal AlGaN Bulk Acoustic Wave Resonators on Silicon Substrates with High Electromechanical Coupling: RFIC Industry Showcase
Ready, Fire, Aim - Highlights of Hot Chips 20
Chief Scientist Barbara De Salvo on How Leti is a Pioneer to Innovation - 2016 Women in Engineering Conference
Transphorm: Redefining Energy Efficiency
22 nm FD-SOI Technology Optimized for RF/mmWave Applications - Steffen Lehmann - RFIC Showcase 2018
KeyTalk with Ljubisa Stevanovic: From SiC MOSFET Devices to MW-scale Power Converters - APEC 2017
Fully-Integrated Non-Magnetic 180nm SOI Circulator - Aravind Nagulu - RFIC Showcase 2018
IEEE WEBINAR SERIES-March 5th, 2014: GaN Crushing Silicon...and Let Me Tell You How
Kurt Petersen: 2019 IEEE Medal of Honor Recipient
Augmented Reality: Stan Honey's Impact on Sports Events and Navigation

IEEE-USA E-Books

  • Plasma-activated bonding, controlled cleave process, and non-contact smoothing for Germanium-on-Insulator (GeOI) manufacturing

    Transistor scaling limitations require profound changes in materials systems used to manufacture future generations of integrated circuits. Germanium-on- Insulator (GeOI) substrates have been proposed as one method to overcome the limitations of silicon and silicon on insulator substrates (SOI). GeOI substrates offer the advantages of the high electron and hole mobilities while at least partially overcoming the high leakage currents inherent to the small band gap of germanium. In addition, GeOI has been found to be compatible with high k gate dielectrics, GeOI is now joining silicon-based materials, including SOI, strained silicon (s-Si), strained silicon on SiGe on insulator (SGOI), or strained silicon on insulator s-SOI as potential next-generation engineered substrates.

  • Thin-film silicon-on-insulator (SOI) device applications of selective epitaxial growth

    Silicon-on-insulator (SOI) technology has surged into a position of prominence in recent years. SOI devices provide a viable technology for high-density, large-scale-integration and high performance VLSI circuits. Of late, the potential applications of SOI devices have extended to the field of power devices and mixed-mode analog-digital circuits. In this field of application in particular, selective epitaxial growth techniques such as epitaxial lateral overgrowth (ELO) and Confined Lateral Selective Epitaxial Growth (CLSEG) provide attractive alternatives to SIMOX. ELO and CLSEG provide the means of selectively growing SOI islands in regions where high performance digital MOS circuitry are desired. Due to the low temperatures involved in selective epitaxy, mixed mode integration becomes a lot easier. This paper presents results from fully-depleted SOI devices fabricated by ELO and provides for the first time a study of interface state densities across the various interfaces in the device. In addition, thin-film fully-depleted SOI devices have been fabricated for the first time in SOI device islands fabricated by CLSEG, and the devices have been used to characterize the material.<<ETX>>

  • An Embedded Silicon-Carbon S/D Stressor CMOS Integration on SOI with Enhanced Carbon Incorporation by Laser Spike Annealing

    We report a CMOS-compatible embedded silicon-carbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to 2.6% substitutional carbon (C<sub>sub</sub>) epitaxial Si:C and laser spike annealing (LSA) for increased C<sub>sub</sub> incorporation. 26% channel resistance (Rch) reduction and 11% Idlin-Ioff enhancement for 0.5% C<sub>sub</sub> and 60% Rch reduction for 2.2% C<sub>sub</sub> are demonstrated.

  • A guided tour of electronic design automation (EDA) for design of silicon on insulator (SOI) SoCs

    The design of SOI-based SoCs has traditionally been the province of a few companies that could afford very labor-intensive custom design approaches - microprocessor companies looking for performance or aerospace companies looking for rad-hard electronics. In recent years, SOI has become a more attractive option for SoC design teams that have traditionally targeted bulk silicon. With current improvements in SOI substrates, processes, devices, design IP and EDA tools, SoC design in SOI can look and feel essentially the same as design in bulk silicon. Designers can use the same familiar EDA tools and flows for bulk silicon, while achieving better performance and power results that are the hallmark of SOI.

  • Twin silicon nanowire FET (TSNWFET) On SOI with 8 nm silicon nanowires and 25 nm surrounding TiN gate

    In this work, fabrication of TSNWFET on SOI with down to 25-nm TiN surrounding gate and 8-nm silicon nanowires is reported with high manufacturability and improved device reliability including reduced junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. And high performance is also obtained to be 1124muA/mum and 1468muA/mum at off current of 1nA/mum for NMOS and PMOS, respectively.

  • Effect of nano-scale strained Si grown on SiGe-on-insulator on electron mobility

    In this paper, we studied experimentally as well as theoretically both effects of strained and nanoscale thickness of top silicon/SiGe-on-insulator on electron mobility.

  • Engineering silicon-on-insulator (SOI) substrates for hybrid orientation technologies (HOT)

    In this paper, deep amorphization of SOI substrate that preserves a crystalline surface layer was demonstrated on (110) and (100) oriented SOI films. The crystalline integrity of the surface layer allowed it to be a template for solid phase epitaxy. At an optimized temperature, pseudo-MOSFET measurements indicate a complete recovery of the electronic properties. However, a small increase is observed for the density of interface states. These results demonstrate the feasibility of this approach to form hybrid (100)/(110) SOI films that would allow increasing the hole mobility.

  • RF SOI CMOS technology on 1st and 2nd generation trap-rich high resistivity SOI wafers

    In this work 3 different types of UNIBOND™ Silicon-on-Insulator (SOI) wafers including one standard and two types of trap-rich high resistivity HR-SOI substrates provided by SOITEC are studied. The DC and RF performances of these wafers are compared by means of passive and active devices, coplanar waveguide (CPW) lines and partially-depleted (PD) SOI MOSFETs, respectively.

  • Electrostatic discharge protection in silicon-on-insulator technology

    Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) semiconductor technology is perceived as a major roadblock for the SOI technology to become a viable mainstream contender for high-performance advanced CMOS semiconductor chips (Hu, 1994; Colinge, 1991). In this paper, our results in four successive SOI technology generations demonstrate that excellent ESD protection levels are achievable in SOI chips with no additional masking steps, process implants, costs or ESD design area. ESD results also show that the ESD robustness of the SOI ESD device is improving with partially depleted SOI MOSFET scaling from 0.25 to 0.12 /spl mu/m L/sub eff/ technology generations (Shahidi et al., 1999; Voldman et al., 1995, 1997, 1999). By allowing the ESD network minimum design to scale with the technology, improved ESD results are evident in each generation with no indication of any SOI- specific ESD limitations. For future technology generations below 1.5 V V/sub DD/ power supply, continued improvement is anticipated due to buried-oxide scaling, lower trigger voltages, dynamic threshold voltage MOSFET (DTMOS) techniques and ESD I/O design learning (Voldman et al, 1997; Assaderaghi et al., 1994). ESD protection of partially depleted SOI technology is not a problem or technology concern using our proposed ESD methodology.

  • Ultra-cut: a simple technique for the fabrication of SOI substrates with ultra-thin (<5 nm) silicon films

    A simple technique for the fabrication of ultra-thin silicon-on-insulator (SOI) substrates is presented. The technique utilizes a combination of two established SOI fabrication procedures and provides a method that eliminates the disadvantages of both. The bond-and-etch-back technique utilizing a Si/sub x/Ge/sub 1-x/ etch stop has been combined with the thin film separation by hydrogen implantation approach for SOI substrate fabrication. Ultra-thin (<5 nm) Si SOI layers have been fabricated successfully and characterized by transmission electron microscopy, atomic force microscopy, and X-ray photoelectron spectroscopy.



Standards related to Silicon On Insulator (SOI)

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