Conferences related to Nonvolatile Memory

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2020 IEEE International Magnetic Conference (INTERMAG)

INTERMAG is the premier conference on all aspects of applied magnetism and provides a range of oral and poster presentations, invited talks and symposia, a tutorial session, and exhibits reviewing the latest developments in magnetism.


2020 Joint Conference of the IEEE International Frequency Control Symposium and International Symposium on Applications of Ferroelectrics (IFCS-ISAF)

Ferroelectric materials and applications


2019 IEEE 11th International Memory Workshop (IMW)

The IMW is a unique forum for specialists in all aspects of memory (nonvolatile & volatile)microelectronics and people with different backgrounds who wish to gain a better understandingof the field. The morning and afternoon technical sessions are organized in a manner thatprovides ample time for informal exchanges amongst presenters and attendees. The eveningpanel discussions will address hot topics in the memory and memory system field. Papers aresolicited in all aspects of semiconductor memory technology (Flash, DRAM, SRAM, PCRAM,RRAM, MRAM, embedded memory, and other NV memories).


2019 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2019 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges.


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Periodicals related to Nonvolatile Memory

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Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


Computer Architecture Letters

Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


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Most published Xplore authors for Nonvolatile Memory

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Xplore Articles related to Nonvolatile Memory

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Fabricated nonvolatile memory with Ag nano-crystals embedded in PVK

2010 2nd IEEE InternationalConference on Network Infrastructure and Digital Content, 2010

We have been researching the polymer nonvolatile memory-cell based on electrical bi-stability. The polymer nonvolatile memory-cell was the 4F2embedded with Ag nano-crystals in conductive polymer. The structure of polymer nonvolatile memory-cell was PVK(poly(N-vinylcarbazole) / Ag nano- crystals / PVK between the Al electrodes. The Ag nano-crystals were formed by using the curing process after evaporate several nanometers of Ag layer. ...


Projected applications, status and plans for Honeywell high density, high performance, nonvolatile memory

Proceedings of Nonvolatile Memory Technology Conference, 1996

The foundation and basis for the Honeywell nonvolatile memory program is the proven, radiation hard, CMOS technology, combined with the proven, radiation hard, MRAM nonvolatile memory technology. These demonstrated capabilities allow the Honeywell team to focus on the most critical elements, the production release of the current AMR nonvolatile products and the development of scalable GMR storage elements capable of ...


2k nonvolatile shadow RAM and 256k EEPROM SONOS nonvolatile memory development

Seventh Biennial IEEE International Nonvolatile Memory Technology Conference. Proceedings (Cat. No.98EX141), 1998

This paper describes SONOS nonvolatile memory development at Sandia National Laboratories. A 256 kbit EEPROM nonvolatile memory and a 2 kbit nonvolatile shadow RAM are under development using an n-channel CMOS/SONOS (complementary metal oxide semiconductor/silicon oxide nitride oxide semiconductor) memory technology. The technology has 1.2 /spl mu/m minimum features in a twin well design using shallow trench isolation.


Static FRAM: an emerging nonvolatile memory technology

Seventh Biennial IEEE International Nonvolatile Memory Technology Conference. Proceedings (Cat. No.98EX141), 1998

Summary form only given. Nondestructively read ferroelectric memories can be achieved using the ferroelectric material as the FET gate oxide. CMOS FETs with ferroelectric gate oxides are very difficult to build but ferroelectric gate TFTs have a robust process that differs from that of the ferroelectric capacitor by only one mask layer. The static FRAM (SFRAM) is one such device. ...


Micro-ball grid arrays: a practical chip-size packaging solution for nonvolatile memory applications

Seventh Biennial IEEE International Nonvolatile Memory Technology Conference. Proceedings (Cat. No.98EX141), 1998

Summary form only given. Increasingly, the package preference of the semiconductor user is the ball grid array (BGA). The array package has gained wide acceptance by the SMT industry due to its improved assembly processing yield. More recently, board design and layout engineers are dramatically increasing the percentage of usable circuit board area by adapting the more miniature chip-scale and ...


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Educational Resources on Nonvolatile Memory

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IEEE.tv Videos

Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
Rebooting Memory Architecture - Wen-mei Hwu at INC 2019
Accelerating Machine Learning with Non-Volatile Memory: Exploring device and circuit tradeoffs - Pritish Narayanan: 2016 International Conference on Rebooting Computing
Magnetic Nanowires: Revolutionizing Hard Drives, RAM, and Cancer Treatment
IMS 2011 Microapps - Memory Effects in RF Circuits: Definition, Manifestations and Fast, Accurate Simulation
From Edge To Core: Memory-Driven Hardware and Software Co-Design - IEEE Rebooting Computing Industry Summit 2017
Ted Berger: Far Futures Panel - Technologies for Increasing Human Memory - TTM 2018
Improved Deep Neural Network Hardware Accelerators Based on Non-Volatile-Memory: the Local Gains Technique: IEEE Rebooting Computing 2017
Impact of Linearity and Write Noise of Analog Resistive Memory: IEEE Rebooting Computing 2017
High-Bandwidth Memory Interface Design
Array storing and retrieval
Robotics History: Narratives and Networks Oral Histories: Barbara Hayes Roth
IRDS: Lithography - Mark Neisser at INC 2019
The Memory of Cars Talk by Tom Coughlin
Memory Centric Artificial Intelligence - Damien Querlioz at INC 2019
RNSnet: In-Memory Neural Network Acceleration Using Residue Number System - Sahand Salamat - ICRC 2018
Quantum Photonic Networks for Computing and Simulation - Plenary Speaker: Ian Walmsley - IPC 2018
IEEE Medal of Honor Recipient (2009): Dr. Robert Dennard
Rajiv V. Joshi - 2018 Daniel E. Noble Award for Emerging Technologies at IEEE ISSCC
Neural Cognitive Robot: Learning, Memory and Intelligence

IEEE-USA E-Books

  • Fabricated nonvolatile memory with Ag nano-crystals embedded in PVK

    We have been researching the polymer nonvolatile memory-cell based on electrical bi-stability. The polymer nonvolatile memory-cell was the 4F2embedded with Ag nano-crystals in conductive polymer. The structure of polymer nonvolatile memory-cell was PVK(poly(N-vinylcarbazole) / Ag nano- crystals / PVK between the Al electrodes. The Ag nano-crystals were formed by using the curing process after evaporate several nanometers of Ag layer. The polymer nonvolatile memory-cell embedded with Ag nano-crystals showed the memory magin(ratio of Ionto Ioff) is ~5.0 × 101. The retention time is more than 105seconds.

  • Projected applications, status and plans for Honeywell high density, high performance, nonvolatile memory

    The foundation and basis for the Honeywell nonvolatile memory program is the proven, radiation hard, CMOS technology, combined with the proven, radiation hard, MRAM nonvolatile memory technology. These demonstrated capabilities allow the Honeywell team to focus on the most critical elements, the production release of the current AMR nonvolatile products and the development of scalable GMR storage elements capable of supporting 4 Gbit/cm/sup 2/ nonvolatile memory technology.

  • 2k nonvolatile shadow RAM and 256k EEPROM SONOS nonvolatile memory development

    This paper describes SONOS nonvolatile memory development at Sandia National Laboratories. A 256 kbit EEPROM nonvolatile memory and a 2 kbit nonvolatile shadow RAM are under development using an n-channel CMOS/SONOS (complementary metal oxide semiconductor/silicon oxide nitride oxide semiconductor) memory technology. The technology has 1.2 /spl mu/m minimum features in a twin well design using shallow trench isolation.

  • Static FRAM: an emerging nonvolatile memory technology

    Summary form only given. Nondestructively read ferroelectric memories can be achieved using the ferroelectric material as the FET gate oxide. CMOS FETs with ferroelectric gate oxides are very difficult to build but ferroelectric gate TFTs have a robust process that differs from that of the ferroelectric capacitor by only one mask layer. The static FRAM (SFRAM) is one such device. It consists of a Pt-PZT capacitor where the top Pt electrode is replaced by a semiconducting oxide. The ferroelectric material polarization state modulates the semiconducting electrode conductivity. The magnitude of the conductivity change can be process controlled to range from 3:1 to 300:1 depending on the product requirements. Current sensing amplifiers can detect the transistor state in as little as 15 ns. Combining one CMOS transistor as the pass gate with each SFRAM transistor, large nonvolatile memory arrays can be built with 40 /spl mu/m/sup 2/ cell sizes, <100 ns cycle times, and using simple SRAM asynchronous three line control. Write operations for SFRAM memory cells are identical to those of the FRAM and have similar power consumption. However, SFRAM source and drain contacts are ohmic, allowing read operations using voltages as low as 50 mV and consuming infinitesimal memory array power. The devices exhibit little fatigue or imprint and can operate with V/sub cc/ as low as 3.5 V. Retention, the most difficult factor to control in ferroelectric transistors, has been demonstrated at 70/spl deg/C. The authors describe the fabrication process for SFRAM devices, provide performance data for discrete transistors measured to date, and show design criteria for a 64 kbit SFRAM.

  • Micro-ball grid arrays: a practical chip-size packaging solution for nonvolatile memory applications

    Summary form only given. Increasingly, the package preference of the semiconductor user is the ball grid array (BGA). The array package has gained wide acceptance by the SMT industry due to its improved assembly processing yield. More recently, board design and layout engineers are dramatically increasing the percentage of usable circuit board area by adapting the more miniature chip-scale and chip-size BGA packaging. Although a relatively new packaging technology, the first qualified product to be offered to the commodity market for flash memory is the chip-size micro-BGA (mBGA) package. By adapting CSP, engineers are not only achieving higher component density but they are also improving overall electrical performance. In this paper, the author details current and future applications of nonvolatile memory using the mBGA package with special focus on standards, reliability issues, materials and the manufacturing process for compliant mBGA and FmBGA packages.

  • Rapid development of MCM-based nonvolatile memory subsystems

    Summary form only given. Information is presented describing a quick-turn multichip module (MCM) technology and its use in the creation of custom nonvolatile memory subsystems. The technology features a programmable MCM substrate as an off-the-shelf solution for rapid circuit development. Two unique applications are discussed in which new designs of EEPROM-based circuits were developed and assembled very quickly. In less than a month, the programs moved from the initial paper concept to assembled, tested, miniaturized hardware. One of the module types experienced a design iteration which was accomplished in less than two days, including upgrading already assembled production units with the design change.

  • Nonvolatile memory requirements in a mobile computing environment

    In order to discuss the nonvolatile memory requirements of mobile systems it is first necessary to define what is meant by "mobile computing environment". This paper begins by distinguishing what is meant by a mobile computing environment and how this environment dictates certain design goals. It is these design goals that are driving two distinct classes of mobile computing products: handheld devices (PDAs, calculators) and mobile computers (notebooks, subnotebooks). These classes are defined in terms of the end-user model on which they are based. It is this end-user model that dictates the architectural requirements of the class. The architecture of the class certainly places demands on the system which in part are being met with nonvolatile memory. The demands that are currently being met with nonvolatile memory are explored for both of the classes of mobile systems. The paper then discusses the current state of the mobile computing environment and how the evolution of this environment will result in the erosion of the architectural differences between the two classes. As the two architectures become less delineated there will be other opportunities for nonvolatile memory. These other opportunities are explored and the role that nonvolatile memory will serve in future mobile systems is discussed.

  • Nonvolatile Memory Characteristics of NMOSFET With Ag Nanocrystals Synthesized via a Thermal Decomposition Process for Uniform Device Distribution

    This paper presents nonvolatile memory characteristics using Ag nanocrystals (NCs) formed by a thermal decomposition and size-selective precipitation technique for Flash memory application. In the NC formation process, the size of NCs and the space NC-to-NC were precisely controlled by a size-selective precipitation technique and the length of the self-assembled monolayer surrounding the NCs, respectively. The size and density of the Ag NCs synthesized were typically 3-5 nm and , respectively. Due to the regularly distributed Ag NCs with high density, uniform memory characteristics and high program efficiency were achieved from NMOSFETs embedded with the Ag NCs, which were fabricated by the gate-last process.

  • Ferroelectric nonvolatile memory technology: applications and integration challenges

    Summary form only given. We discuss different integration approaches, their challenges, and problems specific to the integration of ferroelectric materials into Si-CMOS. The focus is on our ongoing integration efforts using a 1 K test vehicle with 2T/2C memory architectures in single level poly and single level metal with a 0.8 /spl mu/m front-end and a 1.2 /spl mu/m back- end. The ferroelectric capacitor module comprises Pt electrodes and a layered perovskite SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT) dielectric. The capacitor module is integrated between the CMOS front-end and the metal back-end. This approach dictates processing temperatures below 900/spl deg/C during the ferroelectric module processing and below 450/spl deg/C after the metal deposition. Oxide ceramics like SET or PZT are easily damaged in plasma processes. Examples of such process damage and recovery by oxygen anneals are discussed. Progress in patterning capacitor materials is described. Finally, the post-metal anneal dilemma of not being able to perform hydrogen (i.e. forming gas) anneals for transistor recovery is discussed. Ferroelectric capacitor properties and transistor characteristics after integration are shown.

  • Improved Performance of Novel Vertical Assist Operating Select Gate Lateral Coupling Cell for Logic Nonvolatile Memory

    In this letter, we report a high-performance logic nonvolatile memory for pure logic processes using novel structure and operations. Even though a select gate lateral coupling (SGLC) cell has the advantages of small cell size, fast programming speed, and over-erase-free features, it has a critical problem of on-cell current degradation during a relatively small number of program/erase (P/E) cycles. By installing an assist gate (AG) on an SGLC cell and employing novel operation methods, the cycling performance improved significantly from 100 times to 10 k times. The initial purpose of using AG was for Fowler- Nordheim erasing operation. However, it is not only used for erasing operation but also for programming to enhance the coupling ratio using the novel vertical assist (VA) operating method. Owing to the novel VA-SGLC cell structure and combined vertical and lateral coupling operations, it shows enhanced programming speed, wider VTwindow, and higher endurance than the conventional SGLC cell using the same process. As a result, a program time of 10 μs and 10 k times P/E cycling performance, preserving a VT window of over 4 V, is achieved without additional processes or increasing the cell size.



Standards related to Nonvolatile Memory

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Jobs related to Nonvolatile Memory

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