Conferences related to Latch Up

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2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2020 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges


2020 IEEE International Conference on Robotics and Automation (ICRA)

The International Conference on Robotics and Automation (ICRA) is the IEEE Robotics and Automation Society’s biggest conference and one of the leading international forums for robotics researchers to present their work.


2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.


2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)

All areas of ionizing radiation detection - detectors, signal processing, analysis of results, PET development, PET results, medical imaging using ionizing radiation



Periodicals related to Latch Up

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Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Consumer Electronics, IEEE Transactions on

The design and manufacture of consumer electronics products, components, and related activities, particularly those used for entertainment, leisure, and educational purposes




Xplore Articles related to Latch Up

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200 V Superjunction N-Type Lateral Insulated-Gate Bipolar Transistor With Improved Latch-Up Characteristics

IEEE Transactions on Electron Devices, 2013

This paper evaluates the technique used to improve the latching characteristics of the 200 V n-type superjunction (SJ) lateral insulated-gate bipolar transistor (LIGBT) on a partial silicon-on-insulator. SJ IGBT devices are more prone to latch-up than standard IGBTs due to the presence of a strong pnp transistor with the p layer serving as an effective collector of holes. The initial ...


Latch-up in FinFET technologies

2018 IEEE International Reliability Physics Symposium (IRPS), 2018

Low-power FinFET technologies pose new challenges for latch-up safe design. Downscaling of the feature size causes significant drop of the trigger current and holding voltage in the latch-up (LU) victims (standard-cell logic). It is accompanied by an increase of resistance in the wells and tap-connections. The increase of well resistance causes a drop in the efficiency of latch-up guard- rings ...


A latch-up immunized lateral trench-gate conductivity modulated power transistor

Proceedings of the 1999 7th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.99TH8394), 1999

In this paper, a latch-up immunized lateral trench-gate bipolar transistor (LTGBT) is presented, along with its numerical simulations and experimental results. The current at which latch-up occurs in the structure is estimated in comparison with that of the lateral IGBT (LIGBT). The static and dynamic latch-up current densities of the LTGBT were 700 A/cm/sup 2/ and 640 A/cm/sup 2/, respectively. ...


Chip level layout and bias considerations for preventing neighboring I/O cell interaction-induced latch-up and inter-power supply latch-up in advanced CMOS technologies

2005 Electrical Overstress/Electrostatic Discharge Symposium, 2005

CMOS latch-up has historically been a problem in bulk CMOS processes through a parasitic pnpn structure formed by parasitic pnp and npn bipolar transistors. In application systems, latch-up is a dominant failure mode that causes either soft failure due to a loss of data logic states or destructive failure of the system. In this paper, the authors focused on cases ...


Shifting time waveform induced CMOS latch up in bootstrapping technique applications

2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2012

In this study, latch-up mechanisms of the complementary-metal-oxide- semiconductor (CMOS) in bootstrapping technique applied to DC/DC buck converter circuit has been clearly investigated by two dimensional (2D) TCAD simulations. The shifting times of input signal waveforms were demonstrated to be the key factor to induce the CMOS latch-up due to the triggering of parasitic bipolar junction transistors (BJTs) in the ...



Educational Resources on Latch Up

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IEEE-USA E-Books

  • 200 V Superjunction N-Type Lateral Insulated-Gate Bipolar Transistor With Improved Latch-Up Characteristics

    This paper evaluates the technique used to improve the latching characteristics of the 200 V n-type superjunction (SJ) lateral insulated-gate bipolar transistor (LIGBT) on a partial silicon-on-insulator. SJ IGBT devices are more prone to latch-up than standard IGBTs due to the presence of a strong pnp transistor with the p layer serving as an effective collector of holes. The initial SJ LIGBT design latches at about 23 V with a gate voltage of 5 V with a forward voltage drop (V<sub>ON</sub>) of 2 V at 300 A/cm<sup>2</sup>. The latch-up current density is 1100 A/cm<sup>2</sup>. The latest SJ LIGBT design shows an increase in latch-up voltage close to 100 V without a significant penalty in V<sub>ON</sub>. The latest design shows a latch-up current density of 1195 A/cm<sup>2</sup>. The enhanced robustness against static latch-up leads to a better forward bias safe operating area.

  • Latch-up in FinFET technologies

    Low-power FinFET technologies pose new challenges for latch-up safe design. Downscaling of the feature size causes significant drop of the trigger current and holding voltage in the latch-up (LU) victims (standard-cell logic). It is accompanied by an increase of resistance in the wells and tap-connections. The increase of well resistance causes a drop in the efficiency of latch-up guard- rings around aggressors (diffusion at IO). Weak victims and inefficient guard- rings boost the latch-up hazard in FinFET, compared to a planar process. New strategies for latch-up safe design are described.

  • A latch-up immunized lateral trench-gate conductivity modulated power transistor

    In this paper, a latch-up immunized lateral trench-gate bipolar transistor (LTGBT) is presented, along with its numerical simulations and experimental results. The current at which latch-up occurs in the structure is estimated in comparison with that of the lateral IGBT (LIGBT). The static and dynamic latch-up current densities of the LTGBT were 700 A/cm/sup 2/ and 640 A/cm/sup 2/, respectively. These results indicate an improvement of 2.3 times and 4.2 times over those for the LIGBT at the same n/sup +/ cathode length of 5 /spl mu/m. The dependence of the latch-up current density on the design of the n/sup +/ and p/sup +/ cathode regions of the structure is also examined. The maximum controllable current density is found to increase with decreasing space between the trench gate and the p/sup +/ cathode. Specifically, as the space decreases to 2 /spl mu/m, no latch-up phenomenon was observed in our experiment. This remarkable improvement in the latch-up performance is accomplished at the expense of an increase of 0.8 V in the threshold voltage.

  • Chip level layout and bias considerations for preventing neighboring I/O cell interaction-induced latch-up and inter-power supply latch-up in advanced CMOS technologies

    CMOS latch-up has historically been a problem in bulk CMOS processes through a parasitic pnpn structure formed by parasitic pnp and npn bipolar transistors. In application systems, latch-up is a dominant failure mode that causes either soft failure due to a loss of data logic states or destructive failure of the system. In this paper, the authors focused on cases of I/O V<sub>DD</sub> to core V<sub>DD</sub> latch-up and other cross "book" latch-up; the significance of this work shows that in 0.13 and sub-0.13 mum technologies, CMOS latch-up can occur between different V<sub>DD</sub> power supplies and between chip sub-functions. This work advances the CMOS technology by addressing chip-level layout, critical bias considerations, as well as and in conjunction with unit I/O cell level latch-up considerations for preventing neighboring I/O-to-I/O cell interaction-induced latch-up. Additionally, emission microscope (EMMI) techniques and latch-up simulation results were shown.

  • Shifting time waveform induced CMOS latch up in bootstrapping technique applications

    In this study, latch-up mechanisms of the complementary-metal-oxide- semiconductor (CMOS) in bootstrapping technique applied to DC/DC buck converter circuit has been clearly investigated by two dimensional (2D) TCAD simulations. The shifting times of input signal waveforms were demonstrated to be the key factor to induce the CMOS latch-up due to the triggering of parasitic bipolar junction transistors (BJTs) in the CMOS bootstrapping application. In addition, the free latch-up design window suggests that both of the larger rise time and longer shifting times of input signal waveforms will provide a larger safety operation region for circuit design engineers in this work.

  • Buried gate SOI LIGBT without latch-up susceptibility

    Summary form only given. LIGBT (lateral insulated gate bipolar transistor) is a promising device for smart power ICs due to its low forward voltage drop and high input impedance. Also, the SOI structure has several advantages, such as ease of isolation and low leakage currents. However, the LIGBT contains an inherent parasitic thyristor, which turns on when the voltage drop in the p/sup -/ base layer under the n/sup +/ cathode is above 0.7 V. These phenomenon is called latch-up. The FBSOA (forward biased safe operating area) of the LIGBT is limited by this latch-up phenomenon. In order to prevent latch-up, it is important to reduce the voltage drop due to hole currents. In this paper, a thin film SOI LIGBT with buried gate is proposed to suppress latch-up and is verified by numerical simulation. The buried gate and buried oxide are formed by the reverse silicon wafer direct bonding technique (Matsumoto, IEDM Tech. Dig., pp. 949-51, 1996). Also, in order to reduce the voltage drop due to the p/sup -/ base region, a p/sup +/ region is formed. This enables the proposed LIGBT with buried gate to suppress the parasitic thyristor latch-up and enlarge the FBSOA efficiently.

  • A Novel High Latch-Up Immunity Electrostatic Discharge Protection Device for Power Rail in High-Voltage ICs

    In this letter, a novel high latch-up immunity electrostatic discharge protection device that can be equivalent to a PNP-type bipolar junction transistor (BJT) and a series-connected Zener diode is proposed. For the proposed device, the emitter of its BJT is formed by Zener implantation instead of conventional P-plus. In this way, the high latch-up immunity can be achieved by the Zener implantation dose and window designing. Meanwhile, the proposed device exhibits excellent voltage clamp capability and 2.2 times large second breakdown current as a generally used diode.

  • Analysis of the Novel Snapback-Free LIGBT With Fast-Switching and Improved Latch-Up Immunity by TCAD Simulation

    In this letter, a novel snapback-free LIGBT with fast-switching and improved latch-up immunity is proposed and investigated by TCAD simulation. The structure features a shorted-anode NPN (SA NPN) beside the insulated oxide trench in the N-buffer and a lowly doped P-region (PD) alongside the deep- oxide trench (DOT) in the N-drift. The SA NPN provides an effective path of electron extraction and completely suppresses the snapback voltage. The PD changes the transmission path of hole current, makes the distribution of hole current more uniform, and contributes to the depletion of the drift region. As simulation results show, at the same forward voltage drop of 1.40 V, the turn- off time for the proposed SAPD LIGBT is reduced by 36.6% and 57.4%, respectively, compared with SA LIGBT and DOT LIGBT. In addition, compared with DOT LIGBT, breakdown voltage is increased by 7.6% and latch-up voltage is increased by nearly 20% for the proposed SAPD LIGBT.

  • Unusual latch-up phenomenon and a novel solution without an additional cost

    An unusual latch-up phenomenon in a microcontroller with a built-in flash memory was detected. The root cause was identified by TCAD simulation and the latch-up mechanism was explained. A novel solution without additional cost was proposed. After applying this solution, the latch-up immunity was dramatically improved.

  • The Analysis on Transient-Induced Latch-up in output driver circuit

    The occurrence of transient induced latch up (TLU) in output driver circuits is studied. A RS485 transceiver fabricated by a 0.5-μm CMOS process was used for a test chip, and the reason for TLU be induced in output driver circuit is analyzed in this paper, the latch-up and EMMI tests are taken to confirm the reason and position of latch-up.



Standards related to Latch Up

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IEEE Standard for Definitions, Symbols, and Characterization of Floating Gate Memory Arrays

Modify the present FGA standard to include floating gate flash" EEPROM's that use Fowler-Nordheim tunneling and/or hot electron injection programming techniques. Hot electron injection EPROM's are included for completeness."