81 resources related to Device Wearout
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APEC focuses on the practical and applied aspects of the power electronics business. Not just a power designer’s conference, APEC has something of interest for anyone involved in power electronics including:- Equipment OEMs that use power supplies and converters in their equipment- Designers of power supplies, dc-dc converters, motor drives, uninterruptable power supplies, inverters and any other power electronic circuits, equipments and systems- Manufacturers and suppliers of components and assemblies used in power electronics- Manufacturing, quality and test engineers involved with power electronics equipment- Marketing, sales and anyone involved in the business of power electronic- Compliance engineers testing and qualifying power electronics equipment or equipment that uses power electronics
Meeting of academia and research professionals to discuss reliability challenges
20th International Symposium on Quality Electronic Design (ISQED 2019) is the premier interdisciplinary and multidisciplinary Electronic Design conference?bridges the gap among Electronic/Semiconductor ecosystem members providing electronic design tools, integrated circuit technologies, semiconductor technology,packaging, assembly & test to achieve design quality.
ASP-DAC 2019 is the twenty-second annual international conference on VLSI design automation in Asia and South Pacific region, one of the most active regions of design and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC.
Promote the exchange of ideas between academia and industry in the field of computer and networks dependability
Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
IEEE Design & Test of Computers offers original works describing the methods used to design and test electronic product hardware and supportive software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. Topics include IC/module design, low-power design, electronic design automation, design/test verification, practical technology, and standards. IEEE Design & Test of ...
Provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the ...
Publishes original and significant contributions relating to the theory, design, performance and reliability of electron devices, including optoelectronic devices, nanoscale devices, solid-state devices, integrated electronic devices, energy sources, power devices, displays, sensors, electro-mechanical devices, quantum devices and electron tubes.
2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017
Most architectures are designed to mitigate the usually undesirable phenomenon of device wearout. We take a contrarian view and harness this phenomenon to create hardware security mechanisms that resist attacks by statistically enforcing an upper bound on hardware uses, and consequently attacks. For example, let us assume that a user may log into a smartphone a maximum of 50 times ...
2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167), 2001
This paper shows the importance in advanced submicron CMOS technologies of an in-line product monitoring process optimized to screen defects and discover wearout mechanisms. Standby current failures from DRAM modules during accelerated product stresses caused by PMOSFET off conducting hot carrier damage is an observed device wearout mechanism which is not detected by commonly used product defect screens. A product ...
IEEE Photonics Technology Letters, 2000
The DC-bias-induced drift phenomenon in LiNbO/sub 3/ optical intensity modulators is a main cause of device wearout failure. In order to estimate the device lifetime, an activation energy value Ea of the drift is needed, and Ea=1.0 eV is already known for z-cut LiNbO/sub 3/ modulators. However, Ea of x-cut LiNbO/sub 3/ modulators is not known even though there is ...
2011 12th International Symposium on Quality Electronic Design, 2011
A system on a chip (SoC) is becoming smaller and denser. Shrinking transistor size facilitates the integration of functionality on the chip operating at low supply voltage, although this trend lowers the silicon chip reliability. Nevertheless, it is necessary to maintain complete functionality during a long duration, even under changing environments such as temperature fluctuation and/or device wearout: Bias temperature ...
IEEE Transactions on Device and Materials Reliability, 2006
CMOS very large scale integration (VLSI) circuit reliability modeling and simulation have attracted an intense research interest in the last two decades, and as a result, almost all IC reliability simulation tools now try to incrementally characterize the wearout mechanisms of aged devices in iterative ways. These tools are able to accurately simulate the device's wearout process and predict its ...
IMS 2011 Microapps - Advanced Terahertz Device Characterization
LPIRC: On Device Vision, Google AI-Style
IMS 2011 Microapps - Improved Microwave Device Characterization and Qualification Using Affordable Microwave Microprobing Techniques for High-Yield Production of Microwave Components
MicroNano Robotics Enabled Technology for Nano Device Assembly and Drug Discovery
Honda U3-X Personal Mobility Device in NY
Agilent: Test up to 1500 amps and 10,000 volts!
Energous Corporation President Stephen Rizzone demonstrates wireless mobile device charging - 2016 Women in Engineering Conference
CES 2008: Herman Miller's C2 Climate Control for the desktop
Modeling Device-to-Device Communications for Wireless Public Safety Networks - David Griffith - 5G Technologies for Tactical and First Responder Networks 2018
IMS 2012 Microapps - Reducing Active Device Temperature Rise and RF Heating Effects with High Thermal Conductivity Low Loss Circuit Laminates
IMS 2012 Microapps - Panel Session: Device Characterization Methods and Advanced RF/ Microwave Design
Designing Efficient On-Device AI - Aakanksha Chowdhery - LPIRC 2019
26th Annual MTT-AP Symposium and Mini Show - Dr. Ajay Poddar
Multiplication with Fourier Optics Simulating 16-bit Modular Multiplication - Abigail Timmel - ICRC 2018
Micro-Apps 2013: Advances in Load Pull Simulation
Device versus Circuit Engineer
IEEE World Forum on Internet of Things - Milan, Italy - Benjamin Cabe and Charalampos Doukas - IoT Device Management: Using Eclipse IoT Open-Source Tools and Frameworks - Part 3
International Future Energy Challenge (IFEC) 2017
Transportation Electrification: Connected Vehicle Environment
Most architectures are designed to mitigate the usually undesirable phenomenon of device wearout. We take a contrarian view and harness this phenomenon to create hardware security mechanisms that resist attacks by statistically enforcing an upper bound on hardware uses, and consequently attacks. For example, let us assume that a user may log into a smartphone a maximum of 50 times a day for 5 years, resulting in approximately 91,250 legitimate uses. If we assume at least 8-character passwords and we require login (and retrieval of the storage decryption key) to traverse hardware that wears out in 91,250 uses, then an adversary has a negligible chance of successful brute-force attack before the hardware wears out, even assuming real-world password cracking by professionals. M-way replication of our hardware and periodic re- encryption of storage can increase the daily usage bound by a factor of M. The key challenge is to achieve practical statistical bounds on both minimum and maximum uses for an architecture, given that individual devices can vary widely in wearout characteristics. We introduce techniques for architecturally controlling these bounds and perform a design space exploration for three use cases: a limited-use connection, a limited-use targeting system and one-time pads. These techniques include decision trees, parallel structures, Shamir's secret-sharing mechanism, Reed-Solomon codes, and module replication. We explore the cost in area, energy and latency of using these techniques to achieve system-level usage targets given device-level wearout distributions. With redundant encoding, for example, we can improve exponential sensitivity to device lifetime variation to linear sensitivity, reducing the total number of NEMS devices by 4 orders of magnitude to about 0.8 million for limited-use connections (compared with 4 billion if without redundant encoding).
This paper shows the importance in advanced submicron CMOS technologies of an in-line product monitoring process optimized to screen defects and discover wearout mechanisms. Standby current failures from DRAM modules during accelerated product stresses caused by PMOSFET off conducting hot carrier damage is an observed device wearout mechanism which is not detected by commonly used product defect screens. A product screening strategy that takes into account the technology limitations and product stress results is required.
The DC-bias-induced drift phenomenon in LiNbO/sub 3/ optical intensity modulators is a main cause of device wearout failure. In order to estimate the device lifetime, an activation energy value Ea of the drift is needed, and Ea=1.0 eV is already known for z-cut LiNbO/sub 3/ modulators. However, Ea of x-cut LiNbO/sub 3/ modulators is not known even though there is a possibility that the Ea depends on the crystal orientation. Here, Ea=1.4 eV is obtained experimentally for the x-cut LiNbO/sub 3/ modulator with a SiO/sub 2/ buffer layer from their drift measurements between 50/spl deg/C-140/spl deg/C.
A system on a chip (SoC) is becoming smaller and denser. Shrinking transistor size facilitates the integration of functionality on the chip operating at low supply voltage, although this trend lowers the silicon chip reliability. Nevertheless, it is necessary to maintain complete functionality during a long duration, even under changing environments such as temperature fluctuation and/or device wearout: Bias temperature instability must be considered as a time-varying parameter as well. Consequently, techniques that can maintain chip reliability with self-diagnosis and self-repair capabilities are required. In this paper, we propose a dependable SRAM with a built-in self- test that can diagnose and repair itself using wordline and bitcell voltage control. The proposed SRAM comprises memory blocks; each block has independent supply voltages for the wordlines and bitcells. This diagnosis and repair scheme is especially effective for faults that occur in the field. The self- testing capability is available on-line. It is completely transparent to a user, who can use the SRAM with no modification or speed degradation in the memory access protocol. A 1-Mb (64-Kb × 16 blocks) SRAM with the BIST was fabricated with a 65-nm CMOS process and verified. The area overhead is 2.8%.
CMOS very large scale integration (VLSI) circuit reliability modeling and simulation have attracted an intense research interest in the last two decades, and as a result, almost all IC reliability simulation tools now try to incrementally characterize the wearout mechanisms of aged devices in iterative ways. These tools are able to accurately simulate the device's wearout process and predict its impact on the circuit performance. Nevertheless, an excessive simulation time, a tedious device testing work, and a complex parameter extraction process often limit the popularity of these tools in the product design and fabrication stages. In this paper, a new simulation program with integrated circuits emphasis (SPICE) reliability simulation method is developed, which shifts the focus of the reliability analysis from the device wearout to the circuit functionality. A set of accelerated lifetime models and failure equivalent circuit models have been proposed for the most common silicon intrinsic wearout mechanisms, including hot-carrier injection, time-dependent dielectric breakdown, and negative bias temperature instability. The accelerated lifetime models help to identify the most degraded transistors in a circuit in terms of the device's terminal voltage and current stress profiles. Then, the corresponding failure equivalent circuit models are incorporated into the circuit to substitute these identified transistors. Finally, the SPICE simulation is performed again to check the circuit functionality and analyze the impact of the device wearout on the circuit operation. Device individual wearout effect is lumped into a very limited number of SPICE circuit elements within each failure equivalent circuit model, and the circuit performance degradation and functionality are determined by the magnitude of these additional circuit elements. In this new method, it is unnecessary to perform a large number of small-step iterative SPICE simulation process as other tools required to obtain the accuracy. Therefore, the simulation time is obviously shortened. In addition, a reduced set of failure equivalent circuit model parameters, rather than a large number of device SPICE parameters, need to be accurately characterized at each interim wearout process. Thus, the device testing and parameter extraction work are also significantly simplified. These advantages will allow the circuit designers to perform a quick and efficient circuit reliability analysis and to develop practical guidelines for reliable electronic designs
The aggressive technology scaling brings us new challenges, such as parameter variations, soft errors, and device wearout. They increase unreliability of transistors and thus will become a serious problem in SoC designs. To attack these problems, spatial redundancy is commonly utilized. Based on the spatial redundancy, a lot of dual-sensing flip-flops (FFs) are proposed. These FFs require additional circuits consisting of a redundant FF and a comparator. Thus, they suffer large area overhead. In order to reduce the area overhead, this paper proposes a selective replacement method. We focus our attention on a timing-error-predicting FF, named canary FF and evaluate the selective replacement method. We apply it to two commercial processors, Toshiba's MeP and Renesas Electronics's M32R. In the case of MeP, the area overhead is reduced from 55% to 11%.
In this article, we propose two new approaches to improve existing DRM (dynamic reliability management) methodology First, we propose reliability sensors that use small replicated circuits to directly measure device wearout on the chip. A direct degradation measurement by these sensors removes a layer of uncertainty introduced because of inaccurate calibration of the degradation models. Note that, despite using the degradation sensors, we still require the degradation models in order to make reliability projections for the chip's remaining lifetime. Aggressive oxide thickness scaling has caused large vertical electric fields in MOSFET devices, a situation that makes oxide breakdown a crucial issue when supply voltage is not scaled as aggressively as transistor feature size. It therefore becomes increasingly difficult to ensure the reliability of ICs over their lifetime.
The reliability of networks-on-chip (NoC) is threatened by low yield and device wearout in aggressively scaled technology nodes. We propose ReliNoC, a network-on-chip architecture which can withstand failures, while maintaining not only basic connectivity, but also quality-of-service support based on packet priorities. Our network leverages a dual physical channel switch architecture which removes the control overhead of virtual channels (VCs) and utilizes the inherent redundancy within the 2-channel switch to provide spares for faulty elements. Experimental results show that ReliNoC provides 1.5 to 3 times better network physical connectivity in presence of several faults, and reduces the latency of both high and low priority traffic by 30 to 50%, compared to a traditional VC architecture. Moreover, it can tolerate up to 50 faults within an 8×8 mesh at only 10 and 40% latency overhead on control and data packets for PARSEC traces. Synthesis results show that our reliable architecture incurs only 13% area overhead on the baseline 2-channel switch.
Emerging hybrid-CMOS nanoscale devices and architectures offer greater degree of integration and performance capabilities. However, the high power densities, hard error/soft error frequency, process variations, and device wearout affect the overall system reliability. Reactive design techniques, such as redundancy, account for component failures by detecting and correcting the system failures. These techniques incur high area and power overhead. Our research focuses on enhancing the system reliability in hybrid CMOS/Resistive RAM (RRAM) architectures by performing computation in RRAM, whenever the CMOS logic units fail. In particular, we propose dynamically reconfiguring the RRAM cache by mapping the failed CMOS units as look up table (LUT) logic blocks in the RRAM. The proposed approach is validated on a 45nm single core processor with three levels of cache for various SPEC2006 benchmarks. Our results demonstrate that the core is fully functional when failed units are reconfigured in RRAM. Performance degradation of up to one order of magnitude and energy increase of up to two orders of magnitude is observed.
Processes and methodologies for conducting reliability predictions for electronic systems and equipment.
A standardized medium for developing reliability predictions of electronic systems and equipment.