Conferences related to On Chip Protection

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2020 IEEE/PES Transmission and Distribution Conference and Exposition (T&D)

Bi-Annual IEEE PES T&D conference. Largest T&D conference in North America.


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.


2020 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)

The Conference focuses on all aspects of instrumentation and measurement science andtechnology research development and applications. The list of program topics includes but isnot limited to: Measurement Science & Education, Measurement Systems, Measurement DataAcquisition, Measurements of Physical Quantities, and Measurement Applications.


2020 59th IEEE Conference on Decision and Control (CDC)

The CDC is the premier conference dedicated to the advancement of the theory and practice of systems and control. The CDC annually brings together an international community of researchers and practitioners in the field of automatic control to discuss new research results, perspectives on future developments, and innovative applications relevant to decision making, automatic control, and related areas.



Periodicals related to On Chip Protection

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Advanced Packaging, IEEE Transactions on

The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.


Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Communications Magazine, IEEE

IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...


Components and Packaging Technologies, IEEE Transactions on

Component parts, hybrid microelectronics, materials, packaging techniques, and manufacturing technology.



Most published Xplore authors for On Chip Protection

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Xplore Articles related to On Chip Protection

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On-chip protection for automotive integrated circuits robustness

2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS), 2012

On-chip protection architecture for automotive ICs (integrated circuits) system-level robustness is introduced. It comprises three-level protection for interface pins with high bidirectional voltage swing. A first protection stage is optimized to sustain the largest portion of the ESD (electrostatic discharge) and EMI (electromagnetic interference)-induced stress. A second- level protection stage is customized to sustain the relatively lower IC-level ESD stress, ...


On-chip protection in precision integrated circuits operating at high voltage and high temperature

2016 IEEE International Reliability Physics Symposium (IRPS), 2016

A new high voltage swing bipolar ESD (electrostatic discharge) protection device for enabling low leakage precision mixed-signal interface circuits (ICs) operating at high voltage (~ 40 V to 60 V) and high temperature (~125°C to 200°C) is presented. Under these operating conditions, parasitic structures in junction-isolated high voltage process technologies induce unexpected shift in the leakage current over time, leading ...


A New Lateral NPN Transistor Structure for Power MOSFETs with On-Chip Protection

ESSDERC '93: 23rd European solid State Device Research Conference, 1993

Power MOSFETs with built-in shorted load protection featuring a circuit based on a lateral npn transistor (LNPN) have been reported recently, however their performance can be limited by a parasitic vertical npn transistor (VNPN). In this paper a new LNPN structure is presented, which overcomes this problem. A dedicated implant has been introduced to optimize the performance of this new ...


A novel on-chip protection circuit for RFICs implemented in D-mode pHEMT technology

2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2007

This paper presents development of novel circuitry that protects circuits developed in pHEMT technology with minimal impact on RF performance. Reduced on-state resistance, low parasitic capacitance, variable trigger voltage, and small physical size allow the protection circuit to be an attractive solution for ESD protection. Implementation of the circuit in a wideband low noise amplifier (LNA) is presented.


TCAD software for ESD on-chip protection design

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), 2001

Electrostatic discharges (ESD) have always been a serious problem in the semiconductor industry. The presence of high electric fields and the amount of energy dissipated by the semiconductor devices during an ESD can give rise to electric breakdown of sensitive isolation layers as well as local melting, which leads to a latent damage or even breakdown of the whole integrated ...



Educational Resources on On Chip Protection

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IEEE.tv Videos

On-chip Passive Photonic Reservoir Computing with Integrated Optical Readout - IEEE Rebooting Computing 2017
Towards On-Chip Optical FFTs for Convolutional Neural Networks - IEEE Rebooting Computing 2017
IMS 2014:Flip Chip Assembly for Sub-millimeter Wave Amplifier MMIC on Polyimide Substrate
Critical Update: KeyTalk with Cian O'Mathuna
IMS MicroApps: Single Chip LNA on 0.25um SOS for SKA Midband Receiver
Q-Band CMOS Transmitter System-on-Chip - Tim Larocca - RFIC Showcase 2018
Prof. Chee Seng Chan - Intellectual Property Protection for Deep Learning Model
R. Jacob Baker - SSCS Chip Chat Podcast, Episode 4
Shantanu Chakrabartty - SSCS Chip Chat Podcast, Episode 5
IEEE WIE- TryEngineering Ship the Chip
Brooklyn 5G Summit 2014: Erik Starkloff on Platform Approach to Design
ON-CHIP VOLTAGE AND TIMING DIAGNOSTIC CIRCUITS
Useful Quantum Computing - Pete Shadbolt - ICRC San Mateo, 2019
A 10-40GHz Frequency Quadrupler Source with Switchable Bandpass Filters and >30dBc Harmonic Rejection: RFIC Interactive Forum 2017
KeyTalk with Ljubisa Stevanovic: From SiC MOSFET Devices to MW-scale Power Converters - APEC 2017
A 200um x 200um x 100um, 63nW, 2.4GHz Injectable Fully-Monolithic Wireless BioSensing System: RFIC Industry Showcase 2017
Group on Earth Observations(GEOSS): Applications
Heuristics for Design for Reliability in Electrical and Electronic Products
Challenges of Big Data on a Global Scale: 2017 Brain Fuel President's Chat
Abstraction and Modeling of Cyber Security tutorial, Part 1

IEEE-USA E-Books

  • On-chip protection for automotive integrated circuits robustness

    On-chip protection architecture for automotive ICs (integrated circuits) system-level robustness is introduced. It comprises three-level protection for interface pins with high bidirectional voltage swing. A first protection stage is optimized to sustain the largest portion of the ESD (electrostatic discharge) and EMI (electromagnetic interference)-induced stress. A second- level protection stage is customized to sustain the relatively lower IC-level ESD stress, and the third level protection stage absorbs the initial transient voltage impulse.

  • On-chip protection in precision integrated circuits operating at high voltage and high temperature

    A new high voltage swing bipolar ESD (electrostatic discharge) protection device for enabling low leakage precision mixed-signal interface circuits (ICs) operating at high voltage (~ 40 V to 60 V) and high temperature (~125°C to 200°C) is presented. Under these operating conditions, parasitic structures in junction-isolated high voltage process technologies induce unexpected shift in the leakage current over time, leading to malfunction in the precision high voltage input/output interface circuit. A proposed device design addresses the low leakage targets at the mentioned operating conditions, while achieving the required ESD robustness of the high voltage interface for industrial applications.

  • A New Lateral NPN Transistor Structure for Power MOSFETs with On-Chip Protection

    Power MOSFETs with built-in shorted load protection featuring a circuit based on a lateral npn transistor (LNPN) have been reported recently, however their performance can be limited by a parasitic vertical npn transistor (VNPN). In this paper a new LNPN structure is presented, which overcomes this problem. A dedicated implant has been introduced to optimize the performance of this new component. The results of the computer simulations are in good agreement with the experimental data. Power MOSFETs featuring the new component have been fabricated which are protected against load short circuit, overcurrents, ESD and overvoltages.

  • A novel on-chip protection circuit for RFICs implemented in D-mode pHEMT technology

    This paper presents development of novel circuitry that protects circuits developed in pHEMT technology with minimal impact on RF performance. Reduced on-state resistance, low parasitic capacitance, variable trigger voltage, and small physical size allow the protection circuit to be an attractive solution for ESD protection. Implementation of the circuit in a wideband low noise amplifier (LNA) is presented.

  • TCAD software for ESD on-chip protection design

    Electrostatic discharges (ESD) have always been a serious problem in the semiconductor industry. The presence of high electric fields and the amount of energy dissipated by the semiconductor devices during an ESD can give rise to electric breakdown of sensitive isolation layers as well as local melting, which leads to a latent damage or even breakdown of the whole integrated circuit (IC). One measure to prevent the breakdown of the IC is to provide the product with an adequate ESD robustness by implementing a kind of lightning conductor in the form of a protection element on the product itself. This methodology is called on-chip ESD protection.

  • On-chip protection for RF technologies

    None

  • Complete Time-Domain Diode Modeling: Application to Off-Chip and On-Chip Protection Devices

    Protection elements are commonly used in electronic systems: digital integrated circuits (ICs) include built-in electrostatic discharge protection devices, and sensitive lines or printed circuit boards traces are often protected using discrete elements, such as clamping or Zener diodes. In order to know if a perturbation is able to disturb or damage ICs, the actual level of signal entering the digital core of the components must be accurately determined, taking into account all the effects of the protection devices. Thus, assessing the perturbation signal at IC core level requires accurate models of the protection elements, even in the case they are inactive. Therefore, this paper focuses on the experimental and theoretical evaluation of the protective behaviors and parasitic effects of these elements. Some limitations of the standard SPICE diode and IBIS models are discussed, and a modeling methodology is presented. Based on a time-domain characterization method associated with a parameter-extraction procedure for enhanced SPICE diode models, the methodology is applied to both discrete and on-chip protection devices and has a good agreement with measurement.

  • New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance

    A new transient detection circuit for on-chip protection design against system-level electrical-transient disturbance is proposed in this paper. The circuit function to detect positive or negative electrical transients under system-level electrostatic-discharge (ESD) and electrical-fast-transient (EFT) testing conditions has been investigated by HSPICE simulation and verified in silicon chip. The experimental results in a 0.18-μm complementary-metal-oxide- semiconductor (CMOS) process have confirmed that the new proposed on-chip transient detection circuit can successfully memorize the occurrence of system-level electrical-transient disturbance events. The output of the proposed on-chip transient detection circuit can be used as a firmware index to execute the system recovery procedure. With hardware/firmware codesign, the transient disturbance immunity of microelectronic products equipped with CMOS integrated circuits under system-level ESD or EFT tests can be significantly improved.

  • Self-Reset Transient Detection Circuit for On-Chip Protection Against System-Level Electrical-Transient Disturbance

    A new self-reset transient detection circuit for on-chip protection against a system-level electrical-transient disturbance is proposed. This circuit is designed to detect the occurrence of system-level electrical-transient disturbance events, and automatically reset the system to initial state for the next detection. In addition, the reset time can be adjusted to meet the different requests of system recovery time in microelectronic products. The circuit performance has been investigated by HSPICE simulation and verified in silicon chip. The experiment results in a 0.18-μm complementary metal-oxide semiconductor (CMOS) process with 1.8-V devices have confirmed the detection and self-reset functions of the proposed on-chip self-reset transient detection circuit under system-level electrostatic discharge and electrical- fast-transient testing conditions. With firmware co-design, the proposed detection circuit can provide an effective on-chip solution to recover the microelectronic system from the system-level transient disturbance-induced abnormal state to a known stable state. Therefore, the immunity level of microelectronic products equipped with CMOS integrated circuits against electromagnetic susceptibility can be effectively enhanced.

  • The Challenges of On-Chip Protection for System Level Cable Discharge Events (CDE)

    The CDE stress for on-chip protection is evaluated with the design of a TI internal CDE tester. Comparison with a long-pulse TLP indicated non- correlation for the failure current but better tracking with the failure voltage. However, both the on-board magnetics and board design can also influence the failure threshold level.



Standards related to On Chip Protection

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(Replaced) IEEE Standard VHDL Language Reference Manual

his standard revises and enhances the VHDL language reference manual (LRM) by including a standard C language interface specification; specifications from previously separate, but related, standards IEEE Std 1164 -1993,1 IEEE Std 1076.2 -1996, and IEEE Std 1076.3-1997; and general language enhancements in the areas of design and verification of electronic systems.


American National Standard Radiation Protection Instrumentation Test and Calibration ヨ Air Monitoring Instruments

This standard establishes test and calibration requirements for air monitoring instruments used for the detection and measurement of airborne radioactive substances.


IEEE Application Guide for Distributed Digital Control and Monitoring for Power Plants


IEEE Guide for Performing Arc-Flash Hazard Calculations--Amendment 1

The guide provides techniques for designers and facility operators to apply in determining the arc-flash hazard distance and the incident energy to which employees could be exposed during their work on or near electrical equipment. The amendment will correct text errors in Clauses 5.2, last paragraph; Clauses 5.6, 5.7, and 7.1; and an equation error in the spreadsheet based calculator, ...


IEEE Guide for Protective Relay Applications to Distribution Lines

The scope of this guide is to discuss the application and coordination of protection for radial power-system distribution lines. It includes the descriptions of the fundamentals, line configurations, and schemes. In addition to these, the scope includes identification of problems with the methods used in distribution line protection and the solutions for those problems.The scope of this guide is to ...