8,839 resources related to Device Reliability
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Energy conversion and conditioning technologies, power electronics, adjustable speed drives and their applications, power electronics for smarter grid, energy efficiency,technologies for sustainable energy systems, converters and power supplies
ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.
APEC focuses on the practical and applied aspects of the power electronics business. Not just a power designer’s conference, APEC has something of interest for anyone involved in power electronics including:- Equipment OEMs that use power supplies and converters in their equipment- Designers of power supplies, dc-dc converters, motor drives, uninterruptable power supplies, inverters and any other power electronic circuits, equipments and systems- Manufacturers and suppliers of components and assemblies used in power electronics- Manufacturing, quality and test engineers involved with power electronics equipment- Marketing, sales and anyone involved in the business of power electronic- Compliance engineers testing and qualifying power electronics equipment or equipment that uses power electronics
the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.
Meeting of academia and research professionals to discuss reliability challenges
The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.
The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.
Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission
Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.
IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...
Electronics Letters, 1995
A novel In/sub 0.52/(Al/sub 0.9/Ga/sub 0.1/)/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/7As HEMT on InP substrate is proposed and fabricated. By adding 10% Ga to the InAlAs layer, the quality of this quaternary InAlGaAs can be improved. This HEMT demonstrated a peak g/sub m/, of 295 mS/mm, an f/sub T/ of 35 GHz, and an f/sub max/ of 76 GHz with a gate ...
2013 IEEE Conference on Reliability Science for Advanced Materials and Devices, 2013
Reliability in many industries is often given lower priority than device performance or yield. Established unit process metrology is often inadequate to diagnose the root cause of product failures in complex manufacturing processes and a novel approach is required for issue resolution. This paper correlates measurements of crystalline texture and phase made by a fully automated X-ray diffraction tool to ...
2001 IEEE Aerospace Conference Proceedings (Cat. No.01TH8542), 2001
Reliability at high temperatures is one of the most important problems for electronic components operating in extreme space environments. High temperature operation not only reduces the performance of electronic devices, but also greatly shortens their lifetime. The electronic devices are usually designed for room temperature performance. In this paper a review is made of high temperature reliability testing of solid-state ...
2004 IEEE International Reliability Physics Symposium. Proceedings, 2004
The effects of shallow trench isolation (STI)-induced mechanical stress on hot carrier-induced degradation of n-/p-MOSFETs with different source(S)/drain(D) areas and channel widths are studied. It is found that mechanical stress increase with S/D area reduction has no impact on the hot carrier degradation for n-/p-MOSFETs with large channel width. However, hot carrier lifetime can be improved when channel width is ...
2006 IEEE International Integrated Reliability Workshop Final Report, 2006
Power management devices often require operation in the 20 V to 30 V range. A common choice for the power MOS driver is an n-channel lateral DMOS (N-LDMOS) device. An advantage of N-LDMOS device is that it can easily be integrated within existing technologies to handle a wide range of operating voltages without significant process changes. Because of the high ...
IFEC 2011-International Future Energy Challenge 2011
Cryogenics for Applied Superconductivity - ASC-2014 Plenary series - 11 of 13 - Friday 2014/8/15
Arizona Reliability Society - May 1 2015
Heuristics for Design for Reliability in Electrical and Electronic Products
APEC 2015: KeyTalks - How to Optimize Performance and Reliability of GaN Power Devices
IMS 2011 Microapps - Beyond the S-Parameter: The Benefits of Nonlinear Device Models
The Long Term Reliability of Gallium Nitride
IMS 2011 Microapps - Advanced Terahertz Device Characterization
APEC 2015: KeyTalks - US DOE perspective on Microgrids
LPIRC: On Device Vision, Google AI-Style
IMS 2011 Microapps - Improved Microwave Device Characterization and Qualification Using Affordable Microwave Microprobing Techniques for High-Yield Production of Microwave Components
MicroNano Robotics Enabled Technology for Nano Device Assembly and Drug Discovery
Consistent, Reliable and Peak-Performing PCB Assemblies: MicroApps 2015 - Zentech Manufacturing, Inc.
Inventor C++ Bjarne Stroustrup (high resolution)
Honda U3-X Personal Mobility Device in NY
Agilent: Test up to 1500 amps and 10,000 volts!
Energous Corporation President Stephen Rizzone demonstrates wireless mobile device charging - 2016 Women in Engineering Conference
CES 2008: Herman Miller's C2 Climate Control for the desktop
IEEE Green Energy Summit 2015, Panel 2: How reliable is reliable enough?
A novel In/sub 0.52/(Al/sub 0.9/Ga/sub 0.1/)/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/7As HEMT on InP substrate is proposed and fabricated. By adding 10% Ga to the InAlAs layer, the quality of this quaternary InAlGaAs can be improved. This HEMT demonstrated a peak g/sub m/, of 295 mS/mm, an f/sub T/ of 35 GHz, and an f/sub max/ of 76 GHz with a gate length of 0.8 mu m. Furthermore. After 36 h of biasing stress, almost no change in drain current and transconductance was observed in the InAlGaAs HEMT. Which is a better result than obtainable in conventional InP HEMTs.<<ETX>>
Reliability in many industries is often given lower priority than device performance or yield. Established unit process metrology is often inadequate to diagnose the root cause of product failures in complex manufacturing processes and a novel approach is required for issue resolution. This paper correlates measurements of crystalline texture and phase made by a fully automated X-ray diffraction tool to the reliability of Cu interconnects and gate oxide and source/drain contacts with nickel silicide metallization.
Reliability at high temperatures is one of the most important problems for electronic components operating in extreme space environments. High temperature operation not only reduces the performance of electronic devices, but also greatly shortens their lifetime. The electronic devices are usually designed for room temperature performance. In this paper a review is made of high temperature reliability testing of solid-state electronic components. To date, most of this work has been concerned with high temperature stressing, usually for short periods of time (less than 100 hours) to demonstrate stability. Comprehensive high temperature reliability studies will be required to field high temperature devices for future space exploration.
The effects of shallow trench isolation (STI)-induced mechanical stress on hot carrier-induced degradation of n-/p-MOSFETs with different source(S)/drain(D) areas and channel widths are studied. It is found that mechanical stress increase with S/D area reduction has no impact on the hot carrier degradation for n-/p-MOSFETs with large channel width. However, hot carrier lifetime can be improved when channel width is reduced. This hot carrier degradation phenomenon due to STI-induced mechanical stress cannot be explained by piezoresistance effect. Based on the simulation results of mechanical stress distributions at different channel regions and the finding of tensile pocket along STI edge, the mechanism of pattern density effect on hot carrier degradation is also provided.
Power management devices often require operation in the 20 V to 30 V range. A common choice for the power MOS driver is an n-channel lateral DMOS (N-LDMOS) device. An advantage of N-LDMOS device is that it can easily be integrated within existing technologies to handle a wide range of operating voltages without significant process changes. Because of the high voltages applied to the N-LDMOS device hot carrier (HC) degradation is a real reliability concern. In high power applications N-LDMOS devices are often implemented in transistor arrays where the basic cell is a dual gate single drain device. This paper focuses on understanding unusual N-LDMOS HC results in which single gate devices had significantly better HC performance than dual gate devices
High reliability performance of network is essential to minimize the possible network service interruption time, particularly in optical backbone networks where a large amount of data can be affected by a single failure. The existing studies on improvement of network reliability performance assume that failures of network devices are not related to the traffic load, which on the other hand, is not always true. For example, the lifetime of erbium doped fiber amplifier (EDFA) depends on the number of amplified lightpaths passing through. Encouraged by this observation, in this paper, we investigate the impact of used routing and wavelength assignment (RWA) algorithm on the number of failures in the network, and as a consequence on the network operational cost related to the failure reparation. We propose and evaluate a novel RWA approach, referred to as reliability performance aware RWA (RA-RWA), taking into account particular EDFA reliability performance characteristics with the goal of reducing the number of EDFA failures. The assessment results show that the operational cost related to EDFA failure reparation is impacted by the chosen RWA. The proposed RA-RWA provides 6% reduction, while other analyzed RWA algorithm, i.e., least loaded path (LLP), causes significant rise (up to 27%) of EDFA related failure reparation cost compared to the classical shortest path (SP) approach. In addition, RA-RWA offers further benefits in terms of reduced blocking probability compared to the SP. Concluding, we show that considering device reliability performance characteristics in RWA is important for the optical network operators as it can impact the network operational cost related to EDFA failure reparation.
The space community and other high reliability users of microelectronic devices have been derating junction temperature and other critical stress parameters for decades to improve device reliability and extend operating life. Semiconductor technology scaling and process improvements, however, compel us to reassess common failure mechanisms and established derating guidelines to provide affirmation that common derating factors remain adequate for current technologies used in high reliability space applications. It is incumbent upon the user to develop an understanding of advanced technology failure mechanisms through modeling, accelerated testing, and failure analysis prior to product insertion in critical applications. This paper provides a summary of an industry survey on junction temperature derating from key microelectronics suppliers, and offers recommendations to users for temperature derating for reliable operation over time. Background information on established derating factors, and recommendations for safe operating junction temperatures for newer technologies are also presented.
The paper reviews the extent to which sleep mode (SM) green routing strategy in green networking impacts on the reliability as well as lifespan of optical networking devices. We first briefly review green routing, followed by describing a simple model of an end-to-end optical network's operational energy consumption. We later discuss operational energy efficiency versus network device reliability as well as lifespan. The discussion is based on results derived from various related works. Overall, we conclude that SM green routing approaches can achieve good device lifespan/reliability without consuming significantly more operational energy.
This work aims at demonstrating the superiority of a Germanium (Ge) source Double Gate Tunnel Field Effect Transistor (DG-TFET) as compared to a conventional Silicon (Si) source DG-TFET in terms of improved analog characteristics. In particular, the influence of Interface Trap Charges (ITC) present at the dielectric semiconductor interface on the reliability of the device is investigated. In addition, a Gate Material Engineered (GME) Ge source DG-TFET is proposed to improve the device reliability through a modification of the flatband voltage of the device near the source channel junction. A comparative analysis of the influence of ITC on a Ge source DG- TFET and a Ge source DG-TFET with Gate Material Engineering (GME) reveals superior device reliability with the amalgamation of GME onto Ge source DG- TFET.
The dependence of device reliability on the lattice perfectness of the active silicon in the high-density 3D-LSIs containing through-silicon via (TSV) and micro-bump (μ-bump) is extensively investigated using hard X rays at SPring8. The reciprocal lattice space (RLS) data revealed that the Si-lattice structure is highly deteriorated owing to the thermo-mechanical (TM) stress exerted by Cu-TSVs and CuSn μ-bumps, and the local mechanical (LM) stress caused by local deformation. The TM stress caused by 20 μm-width Cu-TSV at 300 °C has introduced (i) ~3 degrees of lattice-tilt (mis-orientation) and (ii) ~8.3 % reduction in lattice space (d) values for Si(004) lattice planes in the 3D-LSI chip. This d change has caused a maximum strain of -0.96 %, which corresponds to -1300 MPa of compressive stress. After the curing, the locally deformed upper thin LSI die with 30 μm thickness witnessed as high as 4.9 % increase in d value, and the lattice tilt amount to 0.65 degree. More importantly, the lower 300 μm-thick active/passive interposer has also experienced the lattice tilt and the change in d to the magnitude of around 0.2 degree and 0.4 %, respectively. We have also observed a degradation in the retention time for the stacked memory chip with a decrease in the chip thickness. The median retention time in the 30 μm-thick DRAM-chip was reduced to one-half the retention period for the 100 μm-thick DRAM chip. We explain this phenomenon by deteriorated Young's modulus values and distorted lattice structures in the ultra-thin LSI Si chip. We were able to minimize the TM stress in the active Si to one-third from that of the initial value by sandwiching an organic stress-absorbing polymer between the dielectric layer and the Ta barrier layer, and the polymer is stable up to 400°C.
The scope of this document is to provide guidance for conducting and assessing reliability predictions (techniques and methods) for electronic products and systems.
Processes and methodologies for conducting reliability predictions for electronic systems and equipment.
This document presents a standard that defines the reliability capability of organizations and identifies the criteria for assessing the reliability capability of an organization. This standard is intended to be usable by all organizations that design, manufacture or procure electrical/electronics components or products. Although the concepts described in this standard could be applied to both hardware and software products, the ...
A standardized medium for developing reliability predictions of electronic systems and equipment.
This project will develop for electronic products and systems a standard set of reliability-program objectives which can be used to express reliability requirements when a customer is contracting with a producer for electronic products.
Semiconductor Laser Device Engineer
Lawrence Livermore National Laboratory