Conferences related to Built In Reliability

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2019 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)

Promote the exchange of ideas between academia and industry in the field of computer and networks dependability


2019 IEEE 17th International Conference on Industrial Informatics (INDIN)

Industrial information technologies


2019 IEEE 58th Conference on Decision and Control (CDC)

The CDC is recognized as the premier scientific and engineering conference dedicated to the advancement of the theory and practice of systems and control. The CDC annually brings together an international community of researchers and practitioners in the field of automatic control to discuss new research results, perspectives on future developments, and innovative applications relevant to decision making, systems and control, and related areas.The 58th CDC will feature contributed and invited papers, as well as workshops and may include tutorial sessions.The IEEE CDC is hosted by the IEEE Control Systems Society (CSS) in cooperation with the Society for Industrial and Applied Mathematics (SIAM), the Institute for Operations Research and the Management Sciences (INFORMS), the Japanese Society for Instrument and Control Engineers (SICE), and the European Union Control Association (EUCA).


2019 IEEE 69th Electronic Components and Technology Conference (ECTC)

premier components, packaging and technology conference


2019 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges.


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Periodicals related to Built In Reliability

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Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Biomedical Engineering, IEEE Transactions on

Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.


Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Communications Letters, IEEE

Covers topics in the scope of IEEE Transactions on Communications but in the form of very brief publication (maximum of 6column lengths, including all diagrams and tables.)


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Most published Xplore authors for Built In Reliability

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Xplore Articles related to Built In Reliability

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Built-in reliability in the Ada programming language

IEEE Conference on Aerospace and Electronics, 1990

It is pointed out that the Ada language has many built-in reliability mechanisms for supporting sophisticated real-time applications. These include: features provided by the language that can be used to make programming more reliable; predefined features that allow the user to built in reliabilities; and a numerical computing environment that increases accuracy and system reliability. Examples and performance constraints are ...


Built-in reliability through sodium elimination

Proceedings of 1994 IEEE International Reliability Physics Symposium, 1994

Minute amounts of sodium can cause semiconductor devices to fail. Wafer processors have steadily reduced sodium content to increasingly low levels in the gate oxide area. However, levels as high as 5E18 cm/sup -3/ are still commonly detected around metal layers in the industry. The industry has until now relied on the BPSG layer to prevent penetration into the active ...


Digital and analog integrated-circuit design with built-in reliability

Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1989

A novel approach to the design of digital and analog VLSI with built-in reliability is presented. Physics-based reliability models for key failure mechanisms in VLSI circuits are used to achieve accurate and efficient circuit-level reliability prediction and improvement. A prototype integrated- circuit reliability simulator (RELY) and experimental results on hot-carrier damage and metal electromigration effects are presented.<<ETX>>


VLSI circuit design with built-in reliability using simulation techniques

IEEE Proceedings of the Custom Integrated Circuits Conference, 1990

The use of reliability assurance and enhancement of integrated circuits in the design of high-performance electronic systems is discussed. Circuit simulators with embedded degradation models can be utilized to accurately predict VLSI reliability due to hot-carrier effects and electromigration. Basic design methods for constructing digital and analog circuit blocks with adequate built-in reliability are presented. Lifetime for DRAM circuitries and ...


Statistical Pattern Recognition and Built-in Reliability Test for Feature Extraction and Health Monitoring of Electronics Under Shock Loads

IEEE Transactions on Components and Packaging Technologies, 2009

The built-in stress test (BIST) is extensively used for diagnostics or identification of failure. The current version of BIST approach is focused on reactive failure detection and provides limited insight into reliability and residual life. A new approach has been developed to monitor product-level damage during shock and vibration. The approach focuses on the pre- failure space and methodologies for ...


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Educational Resources on Built In Reliability

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IEEE-USA E-Books

  • Built-in reliability in the Ada programming language

    It is pointed out that the Ada language has many built-in reliability mechanisms for supporting sophisticated real-time applications. These include: features provided by the language that can be used to make programming more reliable; predefined features that allow the user to built in reliabilities; and a numerical computing environment that increases accuracy and system reliability. Examples and performance constraints are given and discussed.<<ETX>>

  • Built-in reliability through sodium elimination

    Minute amounts of sodium can cause semiconductor devices to fail. Wafer processors have steadily reduced sodium content to increasingly low levels in the gate oxide area. However, levels as high as 5E18 cm/sup -3/ are still commonly detected around metal layers in the industry. The industry has until now relied on the BPSG layer to prevent penetration into the active gate area. This approach is usually effective, but not bulletproof. Pinholes or thin spots in BPSG film still allow sodium ions to seep through. This protective or inter-dielectric layer. As part of a strong commitment to achieve built-in reliability, Siliconix launched a project to totally eliminate sodium from its products. As reported in this paper. We have successfully reduced the presence of sodium down to the SIMS detection level.<<ETX>>

  • Digital and analog integrated-circuit design with built-in reliability

    A novel approach to the design of digital and analog VLSI with built-in reliability is presented. Physics-based reliability models for key failure mechanisms in VLSI circuits are used to achieve accurate and efficient circuit-level reliability prediction and improvement. A prototype integrated- circuit reliability simulator (RELY) and experimental results on hot-carrier damage and metal electromigration effects are presented.<<ETX>>

  • VLSI circuit design with built-in reliability using simulation techniques

    The use of reliability assurance and enhancement of integrated circuits in the design of high-performance electronic systems is discussed. Circuit simulators with embedded degradation models can be utilized to accurately predict VLSI reliability due to hot-carrier effects and electromigration. Basic design methods for constructing digital and analog circuit blocks with adequate built-in reliability are presented. Lifetime for DRAM circuitries and operational amplifiers can be significantly increased through these novel simulation techniques. Several practical VLSI design examples using an integrated-circuit reliability simulator are discussed.<<ETX>>

  • Statistical Pattern Recognition and Built-in Reliability Test for Feature Extraction and Health Monitoring of Electronics Under Shock Loads

    The built-in stress test (BIST) is extensively used for diagnostics or identification of failure. The current version of BIST approach is focused on reactive failure detection and provides limited insight into reliability and residual life. A new approach has been developed to monitor product-level damage during shock and vibration. The approach focuses on the pre- failure space and methodologies for quantification of failure in electronic equipment subject to shock and vibration loads using the dynamic response of the electronic equipment. The presented methodologies are applicable at the system level for the identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in shock and drop of electronic assemblies. Three methodologies have been investigated for feature extraction and health monitoring including development of a new solder- interconnect built-in reliability test, FFT-based statistical-pattern recognition, and time-frequency moments based statistical pattern recognition. The solder-joint built-in reliability test has been developed for detecting high resistance and intermittent faults in operational, fully programmed field programmable gate arrays. Frequency band energy is computed using FFT and utilized as the classification feature to check for damage and failure in the assembly. In addition, the time-frequency analysis has been used to study the energy densities of the signal in both time and frequency domains, and provide information about the time evolution of frequency content of transient- strain signal. Closed-form models and explicit finite-element models have been developed for the eigen frequencies, mode shapes, and transient response of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data from modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock damage to subtle changes in boundary conditions,effective flexural rigidity, and transient strain response has been quantified.

  • Methodology for ULSI LOCOS isolation built-in reliability analysis

    The results of studying the mechanisms of CMOS ULSI LOCOS isolation failures and an effective approach to qualifying the technological processes of isolation manufacturing are presented. The described method for reliability analysis allows one to reveal the potential capability of a current technology.

  • FEM simulations for built-in reliability of innovative Liquid Crystal Polymer-based QFN packaging and Sn96.5Ag3Cu0.5 solder joint

    In this study, Quad Flat No-lead (QFN) cavity package based on LCP and the reliability impact of the package geometry are investigated. A well- established model of Sn96.5Ag3Cu0.5 solder joint fatigue based on the Darveaux's methodology leading to strain energy density estimation is used. A dedicated Design of Experiments (DoE) is performed to assess the optimal thermo-mechanical properties of the LCP package leading to the maximum operating lifetime. A correlation between predicted lifetime results and optimal thermo-mechanical properties of the package is obtained depending on the geometry of the QFN under study.

  • The evaluation of 16-Mbit memory chips with built-in reliability

    Highly defective 16-Mb chips have been stressed under accelerated conditions to test the capability of on-chip error-correction circuits for reliability enhancement. The tradeoff between a manufacturing sort or screen yield and reliability was determined. The soft-error immunity of the trench capacitor technology in conjunction with error correction was also evaluated under accelerated conditions.<<ETX>>

  • Comparative FEM thermo-mechanical simulations for built-in reliability: Surface mounted technology versus embedded technology for silicon dies

    The printed circuit assembly market has been interested in embedded component technology for the last two decades in order to increase both integration density and performance of electronic boards. The objective of this technology is to integrate components, actives and passives, in internal layers of printed circuit boards (PCBs). In addition to the RF performances, the electromagnetic compatibility (EMC) characteristics are improved and the reliability increase. New opportunities in the miniaturization of devices emerge with embedded components technology in a wide range of business areas, as automotive or aeronautics sector. If the embedding of thin film passives in PCBs is now well known, few studies have been performed on active components. The manufacturing process results in stresses on embedded chips due to the assembling method, the temperature and material properties. In the present work, simulations based on Finite Element Method (FEM) have been performed to study the thermo-mechanical behavior of such embedded active components during its operating lifetime. In particular the strain energy density is estimated using a dedicated model for solder joint fatigue based on the Darveaux's methodology. The objective of the present study is to compare the estimated lifetime of solder joints of a surface mounted active component and the same embedded active according to the thermoplastic resin substrate used (for PCB). The influence in operating lifetime of main thermo-mechanical properties, as CTE (Coefficient of thermal expansion) and Young's Modulus, of the resin in embedded package allow to determinate the relevance of use very low CTE resin substrate.

  • Statistical Pattern Recognition and Built-in Reliability Test for Feature Extraction and Health Monitoring of Electronics under Shock Loads

    The built-in stress test (BIST) is extensively used for diagnostics or identification of failure. The current version of BIST approach is focused on reactive failure detection and provides limited insight into reliability and residual life. A new approach has been developed to monitor product-level damage during shock and vibration. The approach focuses is on the pre-failure space and methodologies for quantification of failure in electronic equipment subjected to shock and vibration loads using the dynamic response of the electronic equipment. Presented methodologies are applicable at the system- level for identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in shock and drop of electronic assemblies. Three methodologies have been investigated for feature extraction and health monitoring including development of a new solder-interconnect built-in reliability test, FFT based statistical-pattern recognition, and time-frequency moments based statistical pattern recognition. The solder-joint built-in-reliability-test has been developed for detecting high-resistance and intermittent faults in operational, fully programmed field programmable gate arrays. Frequency band energy is computed using FFT and utilized as the classification feature to check for damage and failure in the assembly. In addition, the Time Frequency Analysis has been used to study of the energy densities of the signal in both time and frequency domain, and provide information about the time-evolution of frequency content of transient-strain signal. Closed-form models have been developed for the eigen-frequencies and mode-shapes of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data from modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock-damage to subtle changes in boundary conditions, effective flexural rigidity, and transient strain response have been quantified. Explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, package falloff and solder ball failure. This allows the physical quantification of solder ball crack damage in the form of confidence values and provides a damage index that can be utilized for the health monitoring of solder interconnects in an electronic assembly.



Standards related to Built In Reliability

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IEEE Standard for Information Technology: Hardcopy Device and System Security

This standard defines security requirements (all aspects of security including but not limited to authentication, authorization, privacy, integrity, device management, physical security and information security) for manufacturers, users, and others on the selection, installation, configuration and usage of hardcopy devices (HCDs) and systems; including printers, copiers, and multifunction devices (MFDs). This standard identifies security exposures for these HCDs and systems, ...



Jobs related to Built In Reliability

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