Conferences related to Arrays

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2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.


2019 44th International Conference on Infrared, Millimeter, and Terahertz Waves (IRMMW-THz)

Science, technology and applications spanning the millimeter-waves, terahertz and infrared spectral regions


2019 IEEE 28th International Symposium on Industrial Electronics (ISIE)

The conference will provide a forum for discussions and presentations of advancements inknowledge, new methods and technologies relevant to industrial electronics, along with their applications and future developments.


2019 IEEE 46th Photovoltaic Specialists Conference (PVSC)

Photovoltaic materials, devices, systems and related science and technology


2019 IEEE 69th Electronic Components and Technology Conference (ECTC)

premier components, packaging and technology conference


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Periodicals related to Arrays

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Advanced Packaging, IEEE Transactions on

The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.


Aerospace and Electronic Systems Magazine, IEEE

The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.


Antennas and Propagation, IEEE Transactions on

Experimental and theoretical advances in antennas including design and development, and in the propagation of electromagnetic waves including scattering, diffraction and interaction with continuous media; and applications pertinent to antennas and propagation, such as remote sensing, applied optics, and millimeter and submillimeter wave techniques.


Antennas and Wireless Propagation Letters, IEEE

IEEE Antennas and Wireless Propagation Letters (AWP Letters) will be devoted to the rapid electronic publication of short manuscripts in the technical areas of Antennas and Wireless Propagation.


Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


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Most published Xplore authors for Arrays

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Xplore Articles related to Arrays

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Synthesizing optimal family of linear systolic arrays for matrix computations

[1988] Proceedings. International Conference on Systolic Arrays, 1988

A method is proposed for designing a family of linear systolic arrays for matrix-oriented problems for which two-dimensional arrays have been designed. The design exhibits a tradeoff between local storage, s, and number of processing elements, n. The arrays are linear, with each processor having storage O(s),1<or=s<or=n, for n*n matrix problems. The input matrices are fed as two-speed data streams ...


IEE Colloquium on 'Circularly Polarised Elements and Arrays' (Digest No.125)

IEE Colloquium on Circularly Polarised Elements and Arrays, 1991

None


Efficient feature extractions by uniform structure threshold logic arrays

[1988] Proceedings. International Conference on Systolic Arrays, 1988

Uniform structure threshold logic arrays (USTA) with multi-inputs and multioutputs are proposed for the efficient extraction of important features from time-series multidimensional signals. The fundamental characteristics of an USTA are examined, showing which features can be extracted. The USTA has been used to vertical, horizontal, 45 degrees , and -45 degrees components of characters.<<ETX>>


Mapping strategy for automatic design of systolic arrays

[1988] Proceedings. International Conference on Systolic Arrays, 1988

A mapping strategy for automatic design of systolic arrays is presented. Algorithms are specified in terms of data dependency and identity, and implementations are specified in terms of data propagation and sequence behavior. By establishing a relation between data propagation and sequence, an optimal mapping strategy is formulated as a problem of finding an integer solution of a set of ...


A systematic approach to the design of modular systolic arrays

[1988] Proceedings. International Conference on Systolic Arrays, 1988

The data dependence method is extended to the design of systolic arrays that are not regular but can be thought of as a combination of basic regular systolic modules. For problems that have an intrinsic modular structure, a strategy based on decomposition into subproblems for which a systolic design can be easily derived is suggested. Thus the major problem of ...


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Educational Resources on Arrays

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IEEE.tv Videos

Array storing and retrieval
Array Representation
Random Sparse Adaptation for Accurate Inference with Inaccurate RRAM Arrays - IEEE Rebooting Computing 2017
Concept of Arrays
Micro-Apps 2013: Design and Simulation of Phased Arrays in VSS
5G mmW Phased Arrays - Future X Radio Panel Talk - Baljit Singh - Brooklyn 5G Summit 2018
A 28GHz CMOS Direct Conversion Transceiver with Packaged Antenna Arrays for 5G Cellular Systems: RFIC Industry Showcase 2017
5G UE Phased Array Design - Future X Radio Panel Talk - Ozge Koymen - Brooklyn 5G Summit 2018
Massive MIMO Active Antenna Arrays for Advanced Wireless Communications: IEEE CAS lecture by Dr. Mihai Banu
mmwave Phased Arrays for 5G Applications - Challenges and Opportunities - Ian Gresham: Brooklyn 5G Summit 2017
A 73GHz PA for 5G Phased Arrays in 14nm FinFET CMOS: RFIC Industry Showcase 2017
Abbas El Gamal accepts the IEEE Richard W. Hamming Medal - Honors Ceremony 2016
Brooklyn 5G - 2015 - Dr. Amitabha Ghosh & Dr. Timothy A. Thomas - 5G Channel Modeling from 6 to 100 GHz: Critical Modeling Aspects and Their Effect on System Design and Performance
The Josephson Effect: The Josephson Volt
Laser Communication From Space Using Superconducting Detectors - ASC-2014 Plenary series - 12 of 13 - Friday 2014/8/15
Day 1, PM Sessions Part 1- Brooklyn 5G Summit 2018
Micro-Apps 2013: Rapid Simulation of Large Phased Array T/R Module Networks
A 10-40GHz Frequency Quadrupler Source with Switchable Bandpass Filters and >30dBc Harmonic Rejection: RFIC Interactive Forum 2017
2011 IEEE Medal for Innovations in Healthcare Technology - Harrison H. Barrett
5G Phased Array Technology - Future X Radio Panel - Brooklyn 5G Summit 2018

IEEE-USA E-Books

  • Synthesizing optimal family of linear systolic arrays for matrix computations

    A method is proposed for designing a family of linear systolic arrays for matrix-oriented problems for which two-dimensional arrays have been designed. The design exhibits a tradeoff between local storage, s, and number of processing elements, n. The arrays are linear, with each processor having storage O(s),1<or=s<or=n, for n*n matrix problems. The input matrices are fed as two-speed data streams using fast and slow channels to satisfy the dependencies in the algorithm. The technique leads to simpler designs with fewer number of processors and improved delay from input to output, compared to a previous family of linear arrays.<<ETX>>

  • IEE Colloquium on 'Circularly Polarised Elements and Arrays' (Digest No.125)

    None

  • Efficient feature extractions by uniform structure threshold logic arrays

    Uniform structure threshold logic arrays (USTA) with multi-inputs and multioutputs are proposed for the efficient extraction of important features from time-series multidimensional signals. The fundamental characteristics of an USTA are examined, showing which features can be extracted. The USTA has been used to vertical, horizontal, 45 degrees , and -45 degrees components of characters.<<ETX>>

  • Mapping strategy for automatic design of systolic arrays

    A mapping strategy for automatic design of systolic arrays is presented. Algorithms are specified in terms of data dependency and identity, and implementations are specified in terms of data propagation and sequence behavior. By establishing a relation between data propagation and sequence, an optimal mapping strategy is formulated as a problem of finding an integer solution of a set of linear equations. This approach provides a uniform framework to design a variety of systolic arrays. An automatic design program and some design examples are presented.<<ETX>>

  • A systematic approach to the design of modular systolic arrays

    The data dependence method is extended to the design of systolic arrays that are not regular but can be thought of as a combination of basic regular systolic modules. For problems that have an intrinsic modular structure, a strategy based on decomposition into subproblems for which a systolic design can be easily derived is suggested. Thus the major problem of the synthesis procedure becomes that of interconnecting the basic modules according to the timing and data-flow constraints that arise from the decomposition of the original problem. The synthesis procedure consists of two steps. The local time and space function is derived for the basic module using standard methodologies, and the global time function is then obtained by imposing additional constraints on the flow of the variables and used to derive the interconnections between the modules. The approach is illustrated on two different problems: 2-D convolution and the shortest path on a layered graph.<<ETX>>

  • New conditions for testability of two-dimensional bilateral arrays

    Different sets of testability conditions for two-dimensional bilateral arrays are presented. Conditions are established with respect to the dependency of the testing process on the signal flow. Each set of testability conditions establishes the controllability and observability of a test vector. These conditions are proved to be applicable under different processing models related to the three inputs of each cell in the array. Complexity issues, such as number of test vectors and time units, are discussed.<<ETX>>

  • Formal derivation of systolic arrays-a case study

    The author exemplifies a conceptual framework, namely, the theory of finite- state machines, for the VLSI design process. He starts from a functional description of the system to be realized and achieves a (semi)systolic array in a formal way. The resulting designs are correct by their mere construction.<<ETX>>

  • Regular processor arrays for matrix algorithms with pivoting

    It is shown how to obtain regular (though nonsystolic) processor arrays for algorithms with pivoting. First, the fact that pivoting algorithms cannot be systolic is established. Then it is shown how regular iterative algorithms can be formulated for the Gaussian elimination algorithm with partial pivoting and how the algorithm can then be implemented on the so-called regular iterative arrays (locally connected arrays of essentially identical processor modules, with register pipelines and/or LIFO (last-in/first-out) buffers in some of the links).<<ETX>>

  • IEE Colloquium on 'Two-Dimensional Optoelectronic Device Arrays' (Digest No.158)

    None

  • IEE Colloquium on 'Phased Arrays' (Digest No.185)

    None



Standards related to Arrays

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IEEE Application Guide for Distributed Digital Control and Monitoring for Power Plants


IEEE Application Guide for Low-Voltage AC Power Circuit Breakers Applied with Separately-Mounted Current-Limiting Fuses

This guide applies to low-voltage ac power circuit breakers of the 635 V maximum voltage class with separately-mounted current-limiting fuses for use on ac circuits with available short-circuit currents of 200 000 A (rms symmetrical) or less. Low-voltage ac fused power circuit breakers and combinations of fuses and molded-case circuit breakers are not covered by this guide. This guide sets ...


IEEE Recommended Practice for Maintenance of DC Overhead Contact Systems for Transit Systems

This recommended practice provides overhead contact system maintenance practices and procedures including maintenance techniques, site inspection and test procedures, and maintenance tolerances, for heavy rail, light rail, and trolley bus systems.


IEEE Standard for Automatic Test Markup Language (ATML) for Exchanging Automatic Test Information via eXtensible Markup Language (XML): Exchanging Test Configuration Information

The scope of this trial-use standard is the definition of an exchange format, using eXtensible Markup Language (XML), for identifying all of the hardware, software, and documentation that may be used to test and diagnose a UUT on an automatic test system (ATS).


IEEE Standard for Local and metropolitan area networks - Secure Device Identity

This standard specifies unique per-device identifiers (DevID) and the management and cryptographic binding of a device to its identifiers, the relationship between an initially installed identity and subsequent locally significant identities, and interfaces and methods for use of DevIDs with existing and new provisioning and authentication protocols.


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Jobs related to Arrays

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