Conferences related to Bias Temperature Instability

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2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2020 IEEE International Reliability Physics Symposium (IRPS)

Meeting of academia and research professionals to discuss reliability challenges


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

The fifth joint EUROSOI-ULIS event will be hosted by IMEP-LaHC in Grenoble, France. The focus of the sessions is on advanced nanoscale devices, including SOI technology.Papers in the following areas are solicited:-Physical mechanisms and innovative SOI-like devices.-New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.-Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.-New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc. Advanced test structures and characterization techniques, reliability and variability assessment techniques for new materials and novel devices.

  • 2018 Joint International EUROSOI Workshop andInternational Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

    The fourth joint EUROSOI-ULIS event will be hosted by the University of Granada in Granada, Spain. The focus of the sessions is on advanced nanoscale devices, including SOI technology. Papers in the following areas are solicited:Physical mechanisms and innovative SOI-like devices.New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.

  • 2017 Joint International EUROSOI Workshop andInternational Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

    EUROSOI-ULIS is a European Conference that resulted from the merging in 2015 of the two sister Conferences: EUROSOI and ULIS. The aim of the EUROSOI-ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale semiconductor-on-insulator and silicon-compatible devices. Papers related to the More Moore, More than Moore and Beyond CMOS research fields (alternative semiconductor and dielectric materials, innovative devices, circuit and system design, etc) are highly encouraged.

  • 2016 Joint International EUROSOI Workshop andInternational Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

    In order to further increase audience and scientific impact, the two sister conferences ULIS and EUROSOI have decided to merge in 2015 and the first joint EUROSOI-ULIS event was a sucess. The aim of the EUROSOI-ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale semiconductor-on-insulator and silicon-compatible devices. Papers corresponding to the More Moore, More than Moore and Beyond CMOS domains (alternative semiconductor and dielectric materials, innovative devices, circuit and system design, etc) are highly encouraged.

  • 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

    The future landscape of the micro-nano-electronics will essentially contain extremely miniaturized fully depleted devices such as planar SOI or narrow FinFETs and nanowires. These aspects were covered in both ULIS and EuroSOI conferences, leading to significant overlap. In order to further increase audience and scientific impact, the two sister conferences have decided to merge in 2015. The aim of the EUROSOI-ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale semiconductor-on-insulator and silicon-compatible devices. Papers corresponding to the More Moore, More than Moore and Beyond CMOS domains (alternative semiconductor and dielectric materials, innovative devices, circuit and system design, etc) are highly encouraged.

  • 2014 15th International Conference on Ultimate Integration on Silicon (ULIS)

    The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modelling, simulation and characterisation of advanced nanoscale silicon and silicon compatible devices for More Moore (CMOS, Memories), More than Moore (Nanosensing, Energy Harvesting, RF, ...) and Beyond-CMOS (Nanowires, CNT, Graphene, Tunnel FET, ...) applications.

  • 2013 14th International Conference on Ultimate Integration on Silicon (ULIS)

    The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modelling, simulation and characterisation of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.

  • 2012 13th International Conference on Ultimate Integration on Silicon (ULIS)

    The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modelling, simulation and characterisation of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.

  • 2011 12th International Conference on Ultimate Integration on Silicon (ULIS)

    ULIS is an annual conference that regroups the European research community working on advanced silicon devices and nanodevices. It has been held annually since 2000. The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modelling, simulation and characterisation of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.

  • 2009 10th International Conference on Ultimate Integration on Silicon (ULIS)

    The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.

  • 2008 9th International Conference on Ultimate Integration on Silicon (ULIS)

    The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale silicon and silicon compatible devices for switches, memory and novel applications such as sensors and bioelectronics.


2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

Process & Device Technologies1. Channel Engineering2. High-k/Metal gate Technology3. Advanced Source/Drain Technology4. Interconnect Technology5. Advanced 3D Integration6. Novel Process Technologies7. Ultra-Thin Body Transistors and Device Variability8. Advanced High-k Metal Gate SoC and High Performance CMOS Platforms 9. CMOS Performance Enhancing and Novel Devices 10. Advanced FinFETs and Nanowire FETs11. CNT, MTJ Devices and Nanowire Photodiodes12. Low- Power and Steep Slope Switching Devices13. Graphene Devices14. Advanced Technologies for Ge MOSFETs15. Organic semiconductor devices and technologies16. Compound semiconductor devices and Technology 17. Ultra High Speed Transistors, HEMT/HBT etc. 18. Advanced Power Devices and Reliability19. Flash Memory20. IT Magnetic RAM21. Resistive RAM


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Periodicals related to Bias Temperature Instability

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Aerospace and Electronic Systems Magazine, IEEE

The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.


Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Dependable and Secure Computing, IEEE Transactions on

The purpose of TDSC is to publish papers in dependability and security, including the joint consideration of these issues and their interplay with system performance. These areas include but are not limited to: System Design: architecture for secure and fault-tolerant systems; trusted/survivable computing; intrusion and error tolerance, detection and recovery; fault- and intrusion-tolerant middleware; firewall and network technologies; system management ...


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Most published Xplore authors for Bias Temperature Instability

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Xplore Articles related to Bias Temperature Instability

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Characteristics and Fluctuation of Negative Bias Temperature Instability in Si Nanowire Field-Effect Transistors

IEEE Electron Device Letters, 2008

In this letter, negative bias temperature instability (NBTI) in silicon nanowire field-effect transistors (SNWFETs) is investigated and found to exhibit some new characteristics that are probably due to the structural nature of nanowires. In long-channel SNWFETs, a fast degradation and a quick saturation of NBTI are observed and discussed. In short-channel SNWFETs, a large fluctuation of NBTI is observed, which ...


Anomalous Negative Bias Temperature Instability Degradation Induced by Source/Drain Bias in Nanoscale PMOS Devices

IEEE Transactions on Nanotechnology, 2008

The effect of source/drain (S/D) bias on the negative bias temperature instability (NBTI) of pMOSFETs is studied. The anomalously enhanced NBTI under S/D bias conditions is observed, which cannot be explained by the conventional reaction-diffusion model. A new mechanism based on the enhanced interfacial dissociation of equivSi-H bonds induced by the energetic holes (the hole energy E<sub>h</sub> is higher than ...


Correlations between plasma induced damage and negative bias temperature instability in 65 nm bulk and thin-BOX FDSOI processes

2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016

We evaluate Plasma Induced Damage (PID) and Negative Bias Temperature Instability (NBTI) by measuring frequency of Ring Oscillators (ROs). Initial frequency degradation by PID from Antenna Ratio (AR) of 500 to 1k are 2.1% and 1.9% in the bulk and thin-BOX FDSOI, respectively. NBTI is accelerated by PID in less than 500 AR which is the upper limit of the ...


Acceptor-like trap effect on negative-bias temperature instability (NBTI) of SiGe pMOSFETs on SRB

2016 IEEE International Electron Devices Meeting (IEDM), 2016

In this work, the oxide electric field (Eox) reduction caused by negatively charged traps is proposed to explain the robustness of SiGe pMOSFETs to negative gate bias temperature instability (NBTI) stress. The high density of negatively charged acceptor-like traps close to the SiGe valance band (E<sub>v</sub>) lowers the E<sub>ox</sub> and reduces the NBTI degradation at fixed overdrive. We demonstrate that ...


Effect of gate length on Negative Bias Temperature Instability of 32nm advanced technology HKMG PMOSFET

2016 IEEE International Conference on Semiconductor Electronics (ICSE), 2016

Negative Bias Temperature Instability (NBTI) has become a key reliability concern in semiconductor industries as devices are scaled down. A simulation study had been done on 32 nm technology node PMOS using Synopsys TCAD Sentaurus simulator tool. This paper presents the effect of gate length on NBTI of 32 nm advanced technology high-k metal gate (HKMG) PMOSFET. The effect on ...


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Educational Resources on Bias Temperature Instability

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IEEE.tv Videos

Analog to Digital Traits
Voltage Metrology with Superconductive Electronics
CES 2008: Herman Miller's C2 Climate Control for the desktop
IMS 2012 Microapps - Reducing Active Device Temperature Rise and RF Heating Effects with High Thermal Conductivity Low Loss Circuit Laminates
AlGaN/GaN Plasmonic Terahertz Detectors
A Low Power High Performance PLL with Temperature Compensated VCO in 65nm CMOS: RFIC Interactive Forum
30 Years to High Temperature Superconductivity (HTS): Status and Perspectives
ISEC 2013 Special Gordon Donaldson Session: Remembering Gordon Donaldson - 7 of 7 - SQUID-based noise thermometers for sub-Kelvin thermometry
A Precision 140MHz Relaxation Oscillator in 40nm CMOS with 28ppm/C Frequency Stability for Automotive SoC Applications: RFIC Interactive Forum 2017
ASC-2014 SQUIDs 50th Anniversary: 1 of 6 Arnold Silver
Data and Algorithmic Bias in the Web - Ricardo Baeza-Yates - WCCI 2016
Piero P Bonissone - Lazy Meta-Learning - Creating Customized Model Ensembles on Demand
How Symmetry Constrains Evolutionary Optimizers: A Black Box Differential Evolution Case Study - IEEE Congress on Evolutionary Computation 2017
A High-Efficiency Linear Power Amplifier for 28GHz Mobile Communications in 40nm CMOS: RFIC Interactive Forum 2017
Micro-Apps 2013: Class F Power Amplifier Design, Including System-to-Circuit-to-EM Simulation
Interaction of ferromagnetic and superconducting permanent magnets - superconducting levitation
High-current HTS cables for magnet applications - ASC-2014 Plenary series - 8 of 13 - Thursday 2014/8/14
MIRAI Program and the New Super-high Field NMR Initiative in Japan - Applied Superconductivity Conference 2018
High Temperature Superconductors (HTS) as Enabling Technology for Sustainable Mobility and Energy Efficiency - Applied Superconductivity Conference 2018
One HTS Josephson Junction, An Array of Applications: Has anything come from HTS devices in the last 30 years?

IEEE-USA E-Books

  • Characteristics and Fluctuation of Negative Bias Temperature Instability in Si Nanowire Field-Effect Transistors

    In this letter, negative bias temperature instability (NBTI) in silicon nanowire field-effect transistors (SNWFETs) is investigated and found to exhibit some new characteristics that are probably due to the structural nature of nanowires. In long-channel SNWFETs, a fast degradation and a quick saturation of NBTI are observed and discussed. In short-channel SNWFETs, a large fluctuation of NBTI is observed, which mainly originates from the ultrasmall gate areas of the short-channel SNWFETs and the statistical nature of randomly trapped charges in the oxide and at the Si/SiO<sub>2</sub> interface. Techniques to suppress the fluctuation and characterize the intrinsic NBTI in ultrasmall SNWFETs are proposed and discussed. A recently developed online gate current method is demonstrated, which effectively alleviates this NBTI fluctuation in SNWFETs.

  • Anomalous Negative Bias Temperature Instability Degradation Induced by Source/Drain Bias in Nanoscale PMOS Devices

    The effect of source/drain (S/D) bias on the negative bias temperature instability (NBTI) of pMOSFETs is studied. The anomalously enhanced NBTI under S/D bias conditions is observed, which cannot be explained by the conventional reaction-diffusion model. A new mechanism based on the enhanced interfacial dissociation of equivSi-H bonds induced by the energetic holes (the hole energy E<sub>h</sub> is higher than the reaction activation energy E<sub>a</sub> of equivSi-H bond dissociation) is proposed to address the observed degradation behaviors. Monte Carlo simulations are used to identify the validity of the new mechanism.

  • Correlations between plasma induced damage and negative bias temperature instability in 65 nm bulk and thin-BOX FDSOI processes

    We evaluate Plasma Induced Damage (PID) and Negative Bias Temperature Instability (NBTI) by measuring frequency of Ring Oscillators (ROs). Initial frequency degradation by PID from Antenna Ratio (AR) of 500 to 1k are 2.1% and 1.9% in the bulk and thin-BOX FDSOI, respectively. NBTI is accelerated by PID in less than 500 AR which is the upper limit of the antenna rule. NBTI correlates with PID and also with initial frequency. The correlation coefficient (CC) between NBTI-induced degradations and the initial frequency is 0.68 in FDSOI, while there is few correlation in bulk (CC = 0.24) because random dopant fluctuation is dominant.

  • Acceptor-like trap effect on negative-bias temperature instability (NBTI) of SiGe pMOSFETs on SRB

    In this work, the oxide electric field (Eox) reduction caused by negatively charged traps is proposed to explain the robustness of SiGe pMOSFETs to negative gate bias temperature instability (NBTI) stress. The high density of negatively charged acceptor-like traps close to the SiGe valance band (E<sub>v</sub>) lowers the E<sub>ox</sub> and reduces the NBTI degradation at fixed overdrive. We demonstrate that trap engineering can be exploited to meet aggressive reliability requirements. Furthermore, it is predicted that there are no reliability issues in the SiGe pMOSFETs comparing with the Si counterparts.

  • Effect of gate length on Negative Bias Temperature Instability of 32nm advanced technology HKMG PMOSFET

    Negative Bias Temperature Instability (NBTI) has become a key reliability concern in semiconductor industries as devices are scaled down. A simulation study had been done on 32 nm technology node PMOS using Synopsys TCAD Sentaurus simulator tool. This paper presents the effect of gate length on NBTI of 32 nm advanced technology high-k metal gate (HKMG) PMOSFET. The effect on the device parameters such as threshold voltage (V<sub>th</sub>), drain current (I<sub>d</sub>) and the lifetime of the device had been studied and discussed in detail. It is found that NBTI is not highly dependent on gate length at low oxide field (E<sub>ox</sub>) while at higher E<sub>ox</sub>, longer gate length is shown to significantly affect the Vth degradation where Vth degradation in longer gate length is found to be lowered by 23.39% compared to the shorter.

  • Defects for random telegraph noise and negative bias temperature instability

    Random Telegraphy Noise (RTN) and Negative Bias Temperature Instability (NBTI) are two important sources of device instability. Their relation is not fully understood and is investigated in this work. We examine the similarity and differences of the defects responsible for them. By following the As-grown- Generation (AG) model proposed by our group, we present clear evidences that the As-grown hole traps (AHTs) are responsible for the RTN of pMOSFETs. AHTs also dominate NBTI initially, but the generated defects (GDs) become increasingly important for NBTI as stress time increases. The GDs, however, do not cause RTN.

  • Degradation caused by Negative Bias temperature instability depending on Body Bias on NMOS or PMOS in 65 nm bulk and thin-BOX FDSOI processes

    Reverse Body Bias (RBB) control on Fully Depleted Silicon On Insulator (FDSOI) with thin Buried OXide (BOX) layer mitigates power consumption on the standby mode. However, Degradation caused by Negative Bias Temperature Instability (NBTI) is changed by RBB. We measure aging degradation of ring oscillators by applying RBB to NMOS or PMOS. In bulk, RBB to PMOS suppresses NBTI-induced degradation because increasing threshold voltage reduces carriers in channel. However, RBB to NMOS does not suppress NBTI-induced degradation because Positive BTI (PBTI) is not dominant in NMOS. In FDSOI, RBB to not only PMOS but also NMOS suppresses NBTI-induced degradation because BOX layer intercepts carriers to flow to substrate.

  • Periodic Bias-Temperature Instability monitoring in SRAM cells

    A method and a circuitry for the periodic monitoring of the Bias-Temperature Instability (BTI) influence on SRAMs are presented in this paper. Periodic BTI monitoring provides the ability to predict failures in the memory operation, due to aging, and early react to avoid them. The proposed scheme is based on a simple, low silicon area overhead, differential ring oscillator that can be easily embedded in a typical SRAM without affecting the normal mode of operation.

  • Plasma Damage-Enhanced Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

    In this letter, a mechanism that will make negative bias temperature instability (NBTI) be accelerated by plasma damage in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is presented. The experimental results confirm that the mechanism, traditionally found in the thin gate-oxide devices, does exist also in LTPS TFTs. That is, when performing the NBTI measurement, the LTPS TFTs with a larger antenna ratio will have a higher degree in degradation of the threshold voltage, effective mobility, and drive current under NBTI stress. By extracting the related device parameters, it was demonstrated that the enhancement is mainly attributed to the plasma-damage-modulated creating of interfacial states, grain boundary trap states, and fixed oxide charges. It could be concluded that plasma damage will speed up the NBTI and should be avoided for the LTPS TFT circuitry design

  • Analysis of Negative Bias Temperature Instability in Body-Tied Low-Temperature Polycrystalline Silicon Thin-Film Transistors

    Negative bias temperature instability (NBTI) degradation mechanism in body- tied low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is analyzed by the charge-pumping (CP) technique. The properties of bulk trap states (including interface and grain boundary trap states) are directly characterized from the CP current. The increase of the fixed oxide charges is also extracted, which has not been quantified in previous studies of NBTI degradation in LTPS TFTs. The experimental results confirm that the NBTI degradation in LTPS TFTs is caused by the generation of bulk trap states and oxide trap states.



Standards related to Bias Temperature Instability

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IEEE Standard for Inertial Sensor Terminology

To review all of the definitions included in the standard and to revise them as required. New terminology will be added to bring the document up to date with current technology.



Jobs related to Bias Temperature Instability

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