Conferences related to Multicore System-on-chip

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2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE International Conference on Consumer Electronics (ICCE)

The International Conference on Consumer Electronics (ICCE) is soliciting technical papersfor oral and poster presentation at ICCE 2018. ICCE has a strong conference history coupledwith a tradition of attracting leading authors and delegates from around the world.Papers reporting new developments in all areas of consumer electronics are invited. Topics around the major theme will be the content ofspecial sessions and tutorials.


2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2019 24th Asia and South Pacific Design Automation Conference (ASP-DAC)

ASP-DAC 2019 is the twenty-second annual international conference on VLSI design automation in Asia and South Pacific region, one of the most active regions of design and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC.


2019 29th International Conference Radioelektronika (RADIOELEKTRONIKA)

The main conference scope is latest development in the area of electronics, signal processingand applications, information technologies and systems, computer modeling, and relateddisciplines.


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Periodicals related to Multicore System-on-chip

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Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


Computer Architecture Letters

Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


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Xplore Articles related to Multicore System-on-chip

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MultiExplorer: A tool set for multicore system-on-chip design exploration

2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2015

This paper proposes MultiExplorer, a new toolset for MPSoCs modelling, experimentation, and design space exploration, by combining fast high- abstraction simulation and low-level physical estimates (power, area, and timing). The MultiExplorer infrastructure takes a range of high and low-level parameters to improve accuracy in the design of a multiprocessor system on a chip. Our toolset results show a viable alternative ...


Implementation of Kalman filter with multicore system on chip using function — Level parallelism

IEEE International Conference on Electro-Information Technology , EIT 2013, 2013

Kalman filter is a very popular estimation technique used widely for linear tracking. It uses a set of noisy data as input and produces state estimates with minimum error rate. This study aims to explore how to implement implicit parallelism in multi-core processor and object tracking with task-level parallelism and Kalman Filter is parallelized on Multi-core system on chip. The ...


On the Development of a Runtime Reconfigurable Multicore System-on-Chip

2012 15th Euromicro Conference on Digital System Design, 2012

Over the last years, several research groups have built reconfigurable systems to obtain high performance at low cost by specializing the computing engine to the computation task. Nowadays, FPGA-based multi-core architectures and reconfigurable computing are widely used for embedded systems, even if the development of complete and efficient solutions on this kind of devices is still quite a complex task. ...


Multicore system-on-chip architecture for MPEG-4 streaming video

IEEE Transactions on Circuits and Systems for Video Technology, 2002

The newly defined MPEG-4 Advanced Simple (AS) profile delivers single-layered streaming video in digital television (DTV) quality in the promising 1-2 Mbit/s range. However, the coding tools involved add significantly to the complexity of the decoding process, raising the need for further hardware acceleration. A programmable multicore system-on-chip (SOC) architecture is presented which targets MPEG-4 AS profile decoding of ITU-R ...


Challenges in software development for multicore System-on-Chip development

2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP), 2012

Multiprocessor Systems-on-Chip (MPSoC)-based platforms are becoming more common in the embedded domain. Such systems are a significant deviation from the homogeneous, uniprocessor architectures that have been traditionally employed by embedded designers, thereby making the software development process to effectively target the platform more challenging. Low-resource embedded systems rely on efficient implementations that are not well supported by traditional solutions based ...


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Educational Resources on Multicore System-on-chip

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IEEE.tv Videos

High Throughput Neural Network based Embedded Streaming Multicore Processors - Tarek Taha: 2016 International Conference on Rebooting Computing
Q-Band CMOS Transmitter System-on-Chip - Tim Larocca - RFIC Showcase 2018
Brooklyn 5G Summit 2014: Erik Starkloff on Platform Approach to Design
A 200um x 200um x 100um, 63nW, 2.4GHz Injectable Fully-Monolithic Wireless BioSensing System: RFIC Industry Showcase 2017
ON-CHIP VOLTAGE AND TIMING DIAGNOSTIC CIRCUITS
On-chip Passive Photonic Reservoir Computing with Integrated Optical Readout - IEEE Rebooting Computing 2017
Silicon Labs' Thunderboard Sense (SLTB001A): Mouser Engineering Bench Talk
Towards On-Chip Optical FFTs for Convolutional Neural Networks - IEEE Rebooting Computing 2017
Computing in the Cambrian Era - ICRC 2018 Plenary, Paolo Faraboschi
IMS 2014:Flip Chip Assembly for Sub-millimeter Wave Amplifier MMIC on Polyimide Substrate
A Recurrent Crossbar of Memristive Nanodevices Implements Online Novelty Detection - Christopher Bennett: 2016 International Conference on Rebooting Computing
Socrates-D: Multicore Architecture for On-line Learning: IEEE Rebooting Computing 2017
Infineon: Innovative Semiconductor Solutions
Design of Monolithic Silicon-Based Envelope-Tracking Power Amplifiers for Broadband Wireless Applications
Critical Update: KeyTalk with Cian O'Mathuna
Micro-Apps 2013: Optimizing Chip, Module, Board Transitions Using Integrated EM and Circuit Design Simulation Software
Transceiver Systems for mmWave Application - Mats Carlsson - RFIC Showcase 2018
Conversion of Artificial Recurrent Neural Networks to Spiking Neural Networks for Low-power Neuromorphic Hardware - Emre Neftci: 2016 International Conference on Rebooting Computing
IMS MicroApps: Single Chip LNA on 0.25um SOS for SKA Midband Receiver
Education for Analog ICs

IEEE-USA E-Books

  • MultiExplorer: A tool set for multicore system-on-chip design exploration

    This paper proposes MultiExplorer, a new toolset for MPSoCs modelling, experimentation, and design space exploration, by combining fast high- abstraction simulation and low-level physical estimates (power, area, and timing). The MultiExplorer infrastructure takes a range of high and low-level parameters to improve accuracy in the design of a multiprocessor system on a chip. Our toolset results show a viable alternative to explore multiprocessor scalability (1-64 cores) on affordable simulation times.

  • Implementation of Kalman filter with multicore system on chip using function — Level parallelism

    Kalman filter is a very popular estimation technique used widely for linear tracking. It uses a set of noisy data as input and produces state estimates with minimum error rate. This study aims to explore how to implement implicit parallelism in multi-core processor and object tracking with task-level parallelism and Kalman Filter is parallelized on Multi-core system on chip. The novelty of this study is the introduction of Adaptive Load Balancing Approach (ALBA) to compute the nonrecursive algorithm. This approach can be applied on all form of multicore computers. The parallel Kalman Filter is developed in C# for multicore using .Net framework 4.0. It uses combination of C and CUDA for its implementation on GPU.

  • On the Development of a Runtime Reconfigurable Multicore System-on-Chip

    Over the last years, several research groups have built reconfigurable systems to obtain high performance at low cost by specializing the computing engine to the computation task. Nowadays, FPGA-based multi-core architectures and reconfigurable computing are widely used for embedded systems, even if the development of complete and efficient solutions on this kind of devices is still quite a complex task. Within this context, what seems to be neglected so far is the combination of a multicore architecture with reconfigurable abilities to vary at runtime not only the hardware components but also the number of the available processors. The variation of the number of processors available on the device can be performed in a dynamic way by using the proposed solution, based on a partial bitstream, characterized by the presence of a reconfigurable system in which both components and component memories can be reconfigured at run-time. This paper presents a study of the viability of making a scalable and flexible multicore System-on-Chip (MPSoC) based on customizable reconfigurable processors, called Multi-Adaptive Reconfigurable Core (MARC), providing the communication infrastructures and the memory management required to create such a complex system-on-chip.

  • Multicore system-on-chip architecture for MPEG-4 streaming video

    The newly defined MPEG-4 Advanced Simple (AS) profile delivers single-layered streaming video in digital television (DTV) quality in the promising 1-2 Mbit/s range. However, the coding tools involved add significantly to the complexity of the decoding process, raising the need for further hardware acceleration. A programmable multicore system-on-chip (SOC) architecture is presented which targets MPEG-4 AS profile decoding of ITU-R 601 resolution streaming video. Based on a detailed analysis of corresponding bitstream statistics, the implementation of an optimized software video decoder for the proposed architecture is described. Results show that overall performance is sufficient for real-time AS profile decoding of ITU-R 601 resolution video.

  • Challenges in software development for multicore System-on-Chip development

    Multiprocessor Systems-on-Chip (MPSoC)-based platforms are becoming more common in the embedded domain. Such systems are a significant deviation from the homogeneous, uniprocessor architectures that have been traditionally employed by embedded designers, thereby making the software development process to effectively target the platform more challenging. Low-resource embedded systems rely on efficient implementations that are not well supported by traditional solutions based on architecture virtualisation or middleware. Within this paper we examine these challenges and discuss ways in which they can be mitigated. In particular, we focus on the contributions made by two recent approaches based on Model-Driven Engineering (MDE). We also discuss challenges for future research.

  • A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture

    System design, especially for low power embedded applications often profit from a heterogeneous target hardware platform. The application can be partitioned into modules with specific requirements e.g. parallelism or performance in relation to the provided hardware blocks on the multicore hardware. The result is an optimized application mapping and a parallel processing with lower power consumption on the different cores on the hardware. This paper presents a heterogeneous platform consisting of a microprocessor and a field programmable gate array (FPGA) connected via a standard AMBA bus. The novelty of this approach is that the FPGA is realized as virtual reconfigurable hardware upon a traditional off the shelf FPGA device. The advantage with this approach is that the specification of the virtual FPGA stays unchanged, independent to the underlying hardware and provides therefore features, which the exploited physical host FPGA cannot provide. A special feature of the presented virtual FPGA amongst others is the dynamic reconfigurability which is for example not available with all off the shelf FPGAs. Furthermore the concept of FPGA virtualization enables the re-use of hardware blocks on other physical FPGA devices. This paper presents the hardware platform and describes the tool chain for the heterogeneous system on chip.

  • Radiation tolerant heterogeneous Multicore “system on chip” with built-in multichannel SpaceFibre switch for onboard data management and mass storage device: Components, short paper

    The article presents a 180nm CMOS Radiation tolerant heterogeneous Multi-core ASIC MCT-04 as the SoC (System-on-Chip) with built-in multichannel multiprotocol SpaceFibre/ GigaSpaceWire (SpaceWire-RUS standard), SpaceWire based switch for the onboard data and Mass Storage Device management. The SoC design and architecture support Single-Event-Upset (SEU) fault-tolerant. The MCT-04 embedded networking subsystem provides multiple ports for high-rate interconnection with combination of SpaceWire/ /GigaSpaceWire (SpaceWire- RUS)/SpaceFibre links. Input and processed data streams transmitted via 1.25 Gbps four multiprotocol SpaceFibre/GigaSpaceWire links with built-in DMA controllers. Two SpaceWire links (ECSS-E-50-12C) provide data transfer bandwidth 2-400 Mbps. The MCT-04 embedded networking subsystem on the base SpaceWire/GigaSpaceWire/SpaceFibre provides a balance between external and internal data throughput especially for the multifunctional micro and nanosatellites systems.

  • Radiation tolerant heterogeneous Multicore “system on chip” with built-in multichannel SpaceFibre switch for the “intelligent” signals and images processing systems

    The article presents a Radiation tolerant heterogeneous Multi-core ASIC MC- 30SF6 as the SoC (System-on-Chip) for the onboard “intelligent” signals and images processing systems. MC-30SF6 based on a CMOS 180nm Radiation tolerant library and consists of the five ELVEES IP - cores for the processing and compression data with extra performance more than 9 GFLOPs. The SoC design and architecture support fault tolerance against SEU errors. SoC has built-in multichannel multiprotocol SpaceFibre/GigaSpaceWire (SpaceWire-RUS standard)/SpaceWire embedded networking subsystem. The networking subsystem provides multiple ports for high-rate interconnection with combination of SpaceWire/GigaSpaceWire/SpaceFibre links. SoC support four ports GigaSpaceWire/two ports SpaceWire switch. Input and processed data streams transmitted via 1.25 Gbps two multiprotocol SpaceFibre/GigaSpaceWire and four GigaSpaceWire links. Two SpaceWire links (ECSS-E-50-12C) provide data transfer bandwidth from 2 up to 400 Mbps. The MC-30SF6 embedded networking subsystem on the base SpaceWire/GigaSpaceWire/SpaceFibre provide a balance between ASIC throughput and SoC performance especially for the multifunctional micro and nanosatellites systems.

  • Hardware / Software Virtualization for the Reconfigurable Multicore Platform

    This paper presents the Flex Tiles approach for the virtualization of hardware and software for a reconfigurable multicore architecture. The approach enables the virtualization of a dynamic tile-based hardware architecture consisting of processing tiles connected via a network-on-chip and a reconfigurable FPGA- based layer for application acceleration.

  • A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing

    Convolutional neural networks (CNNs) have revolutionized computer vision, speech recognition, and other fields requiring strong classification capabilities. These strengths make CNNs appealing in edge node Internet-of- Things (IoT) applications requiring near-sensors processing. Specialized CNN accelerators deliver significant performance per watt and satisfy the tight constraints of deeply embedded devices, but they cannot be used to implement arbitrary CNN topologies or nonconventional sensory algorithms where CNNs are only a part of the processing stack. A higher level of flexibility is desirable for next generation IoT nodes. Here, we present Mia Wallace, a 65-nm system-on-chip integrating a near-threshold parallel processor cluster tightly coupled with a CNN accelerator: it achieves peak energy efficiency of 108 GMAC/s/W at 0.72 V and peak performance of 14 GMAC/s at 1.2 V, leaving 1.2 GMAC/s available for general-purpose parallel processing.



Standards related to Multicore System-on-chip

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IEEE Standard Test Interface Language (STIL) for Digital Test Vector Data---Core Test Language (CTL)

Unless the logic inside embedded cores can be merged with the surrounding user-defined logic (UDL), the SoC test requires reuse of test data and test structures specific to individual cores (designs) when integrated into larger systems. This standard defines language constructs sufficient to represent the context of a core and of the integration of that core into a system, to ...


Standard Testability Method for Embedded Core-based Integrated Circuits

IEEE Std 1500 has developed a standard design-for-testability method for integrated circuits (ICs) containing embedded nonmergeable cores. This method is independent of the underlying functionality of the IC or its individual embedded cores. The method creates the necessary requirements for the test of such ICs, while allowing for ease of interoperability of cores that may have originated from different sources.



Jobs related to Multicore System-on-chip

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