138 resources related to Chip Repair
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The conference program will consist of plenary lectures, symposia, workshops and invitedsessions of the latest significant findings and developments in all the major fields of biomedical engineering.Submitted full papers will be peer reviewed. Accepted high quality papers will be presented in oral and poster sessions,will appear in the Conference Proceedings and will be indexed in PubMed/MEDLINE.
The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
The Conference focuses on all aspects of instrumentation and measurement science andtechnology research development and applications. The list of program topics includes but isnot limited to: Measurement Science & Education, Measurement Systems, Measurement DataAcquisition, Measurements of Physical Quantities, and Measurement Applications.
ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.
International Test Conference, the cornerstone of TestWeek events, is the premier conference dedicated to the electronic test of devices, boards, and systems -- covering the complete cycle from design verification, test, diagnosis, failure analysis, and back to process improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment designers, and test engineers.
The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.
Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission
Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.
Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...
Proceedings. International Test Conference, 2002
This paper describes a novel on chip repair system designed for ATE independent application on many unique very dense ASIC devices in a high turnover environment. During test, the system controls on chip built-in self- test (BIST) engines, collects and compresses repair data, programs fuses and finally decompresses and reloads the repair data for post fuse testing. In end use ...
1991 Proceedings 41st Electronic Components & Technology Conference, 1991
A fluxless repair process for flip-chip multichip modules (MCMs) is demonstrated. The process includes steps for removing defective chips, reducing and leveling solder at the chip site, and retacking a new, good chip in its place. After chip removal, most of solder remained on the bonding pads. A technique has been developed to remove excess solder and to level the ...
Proceedings of the IEEE, 2002
Link processing with individual laser pulses has become an industry standard process in IC memory chip manufacturing. It is gaining wide acceptance in analog chip reprogramming and tuning as well. Traditional laser processing, using the standard output of Nd:YAG at 1.064-/spl mu/m and Nd:YLF at 1.047-/spl mu/m laser wavelengths, works well for polysilicon links but is not satisfactory for metal ...
Fifth IEEE/CHMT International Electronic Manufacturing Technology Symposium, 1988, 'Design-to-Manufacturing Transfer Cycle, 1988
Summary form only given. Design mistakes may appear during the validation steps of integrated circuits. Designers need a machine able to modify the interconnection network in an IC prototype during tests. A repair process by laser direct writing of microstructure was achieved via local decomposition of gases in submicron areas on IC chips. Experimental procedures for conductor (Ni) or insulator ...
1995 Proceedings. 45th Electronic Components and Technology Conference, 1995
Underfill encapsulation has been proven to yield dramatic improvement in the fatigue reliability of flip-chip mounted packages on ceramics as well as organic chip carriers. However, lack of reworkability of the underfill epoxy has limited its application to single chip modules or a few simpler multi-chip packages. Reworkability is needed for all expensive multi-chip packages in order to replace the ...
On-chip Passive Photonic Reservoir Computing with Integrated Optical Readout - IEEE Rebooting Computing 2017
IMS 2014:Flip Chip Assembly for Sub-millimeter Wave Amplifier MMIC on Polyimide Substrate
Towards On-Chip Optical FFTs for Convolutional Neural Networks - IEEE Rebooting Computing 2017
IMS 2012 Microapps - Electrical Thermal Coupled Solutions for Flip Chip Designs
Introduction to Chip Multiprocessor Architecture
IMS 2011 Microapps - Improved Soldering Techniques for Cylindrical RF Connectors Using HIG Induction Technology
Critical Update: KeyTalk with Cian O'Mathuna
Micro-Apps 2013: Optimizing Chip, Module, Board Transitions Using Integrated EM and Circuit Design Simulation Software
IMS MicroApps: Single Chip LNA on 0.25um SOS for SKA Midband Receiver
Why Power Supplies Fail: A Real World Analysis - David Hill at APEC 2016
Q-Band CMOS Transmitter System-on-Chip - Tim Larocca - RFIC Showcase 2018
R. Jacob Baker - SSCS Chip Chat Podcast, Episode 4
Shanthi Pavan - SSCS Chip Chat Podcast, Episode 3
Transceiver Systems for mmWave Application - Mats Carlsson - RFIC Showcase 2018
Alice Wang - SSCS Chip Chat Podcast, Episode 6
IEEE WIE- TryEngineering Ship the Chip
Shantanu Chakrabartty - SSCS Chip Chat Podcast, Episode 5
A Wideband SiGe BiCMOS Transceiver Chip-Set for High-Performance Microwave Links in the 5.643.5GHz Range: RFIC Industry Showcase 2017
Useful Quantum Computing - Pete Shadbolt - ICRC San Mateo, 2019
This paper describes a novel on chip repair system designed for ATE independent application on many unique very dense ASIC devices in a high turnover environment. During test, the system controls on chip built-in self- test (BIST) engines, collects and compresses repair data, programs fuses and finally decompresses and reloads the repair data for post fuse testing. In end use applications this system decompresses and loads the repair data at power- up or at the request of the system.
A fluxless repair process for flip-chip multichip modules (MCMs) is demonstrated. The process includes steps for removing defective chips, reducing and leveling solder at the chip site, and retacking a new, good chip in its place. After chip removal, most of solder remained on the bonding pads. A technique has been developed to remove excess solder and to level the pads to a consistent bump height. Experimentation has shown that the wick chip reduced remaining solder bump heights to about the same height as the virgin substrate. New chips were then retacked to the leveled sites and the modules were heated in a controlled atmosphere to reflow the solder joints. Modules repaired using this technique have shown yields similar to those obtained during the initial assembly stages in electrical continuity tests.<<ETX>>
Link processing with individual laser pulses has become an industry standard process in IC memory chip manufacturing. It is gaining wide acceptance in analog chip reprogramming and tuning as well. Traditional laser processing, using the standard output of Nd:YAG at 1.064-/spl mu/m and Nd:YLF at 1.047-/spl mu/m laser wavelengths, works well for polysilicon links but is not satisfactory for metal links. This paper describes the physics modeling and computer simulation of the laser link process and a new technique of using 1.3-/spl mu/m laser wavelength for the process. While light absorption of link materials at 1.064-, 1.047-, and 1.3-/spl mu/m wavelengths are relatively the same, the absorption of a Si substrate at 1.3 /spl mu/m is considerably less. The improved absorption contrast between the link material and silicon substrate at 1.3-/spl mu/m delivers a much wider laser process window. Both simulation and experimental results are given and discussed. A brief introduction of another new technique, which uses UV laser pulses for link processing, is given. This UV laser process delivers a laser beam spot size much smaller than 1.5 /spl mu/m.
Summary form only given. Design mistakes may appear during the validation steps of integrated circuits. Designers need a machine able to modify the interconnection network in an IC prototype during tests. A repair process by laser direct writing of microstructure was achieved via local decomposition of gases in submicron areas on IC chips. Experimental procedures for conductor (Ni) or insulator (Si/sub 3/N/sub 4/) deposition and microelectronic material (SiO/sub 2/-Al) etching were defined. This work led to a VLSI repair machine gathering all these elementary reactions in one process, allowing designers to modify quickly and efficiently interconnection networks.<<ETX>>
Underfill encapsulation has been proven to yield dramatic improvement in the fatigue reliability of flip-chip mounted packages on ceramics as well as organic chip carriers. However, lack of reworkability of the underfill epoxy has limited its application to single chip modules or a few simpler multi-chip packages. Reworkability is needed for all expensive multi-chip packages in order to replace the defective chip with a new one. The rework process for an encapsulated flip chip package is complicated due to factors such as localized chip removal, solder replenish, new chip joining, encapsulation and establish reliability. In this context, the authors have done technical evaluations on a few selected chip repair schemes, such as mechanical chip-grinding, mold release layer, and reworkable epoxy underfill materials. They were studied on metallized ceramic pin grid array modules used as test vehicles. Thermal cycling reliability experiments as well as rework feasibility evaluations were done on test vehicles. Results are briefly presented in this paper.
The use of lasers for thermal processing of materials has been studied extensively [1,2]. Their use in integrated circuit processing has been limited mainly to material removal (resistor trimming, metal delineation, etc.) . This paper describes a recently discovered process in which nanosecond dye laser pulses are used to form reliable low resistance ohmic contacts between conductors on integrated circuit chips. In particular, connections have been formed between the aluminum and diffused silicon layers of a conventional MOS structure (Fig. 1). The key to the connection process is the use of short laser pulses (2-6 ns) which are capable of redistributing materials in a microscopic region without damaging heat sensitive structures surrounding that region. This process of connecting initially isolated structures makes it possible to personalize integrated circuit chips after fabrication without the use of high voltages, high currents or decoding circuitry. Moreover the process allows isolation of propagating faults such as short circuits. The rapid turnaround time of this approach is attractive for ROS and PLA personalization  and makes chip repair and the interconnecting of good working parts at the chip or wafer level possible. The purpose of this paper is to describe experimental studies of these laser formed connections with an emphasis on the mechanism, reliability and reproducibility of the process.
With technologies shrinking and design complexity increasing, it becomes crucial that embedded in chip test and repair solutions keep up with the advances in order to consistently provide superior chip quality and yield optimization. The embedded test approaches developed for designs done a few years ago are not sufficient for today's designs, which are bigger, faster, hierarchical and much more sensitive to area, timing and power. Similarly, the embedded test solutions developed e.g. for 28-nm technology nodes will not deliver the same level of test quality, diagnosis accuracy and repair efficiency for 14-nm technology nodes, as defects and failure mechanisms change with process technologies shrink.
The authors present a defect-tolerant and fully testable programmable logic array (PLA) that is based on dynamic redundancy, allowing for the repair of a defective chip. Special emphasis is placed on the location of defects inside a PLA. The repair process consists of replacing a defect product term by a programmable spare one.<<ETX>>
We demonstrate a new, low-cost, additive aerosol jet (AJ) printing fabrication method for 3-D on-chip interconnects on III-V semiconductor chips. A dielectric layer and bridge-type gold interconnects were printed on a GaAs- based microwave monolithic integrated circuit (MMIC) to connect a gate pad and a ground pad of the MMIC. The MMICs with the printed 3-D interconnects show the same RF performance as those tested before printing with the gate voltage biased at 0 V. This indicates that the 3-D printed interconnects can provide effective and reliable connections. Extensive reliability tests including thermal shock, thermal cycle, and current stress tests were performed on the MMIC with the printed 3-D interconnects. No performance degradation was found after the reliability tests. The performance and reliability study demonstrates that the low-cost, additive 3-D AJ printing is an effective fabrication method for adding highly reliable on-wafer circuit functionalities and features. Additive printing is an excellent complementary technology to existing semiconductor technologies for instantaneous on-wafer circuit prototyping, repair, tuning, reconfiguration, and system on-chip integration with high reliability.
Due to increasing semiconductor design complexity, more errors are escaping presilicon verification and being discovered only after manufacturing. As an alternative to traditional manual chip repair, the authors propose the FogClear methodology, which automates the postsilicon debugging process and thereby reduces IC development time and costs.
This guide recommends procedures to be used to perform failure investigations of power circuit breakers. Although the procedure may be used for any circuit breaker, it is mainly focused on high-voltage ac power circuit breakers used on utility systems. Recommendations are also made for monitoring circuit breaker functions as a means of diagnosing their suitability for service condition.
This document provides guidelines for the definition of a reliability program at nuclear power generating stations. The document emphasizes reliability programs during the operating phase of such stations; however, the general approach applies to all phases of the nuclear power generating station life cycle (e.g., design, construction, start-up, operating, and decommissioning).
This guide provides a list of factors to consider when planning, designing, permitting, installing, commissioning and repairing submarine power cable systems. While many factors are common to both power and communication cable, this guide focuses on power cables.