Conferences related to Yield-enhancement Redundancy

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2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.


2018 IEEE European Test Symposium (ETS)

The scope of the conference is electronic-based circuits and system testing, including VLSI Test, VLSI Reliability, Yield, diagnosis, DFX, Verification, etc.


2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

*RF, analog and mixed-signal circuits*Sensors and interface circuits*Digital circuits and ASIC*CPU, DSP and multicore architectures*Memory circuits and systems*Low power logic and architectures*Multimedia processing circuits*Communication circuits*Embedded systems and software*Designs using novel technologies*System-in-package design*Electronic System Level Design*Modeling and simulation*Hardware-software co-design*Logic and architecture synthes


2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)

ASP-DAC 2018 is the 23rd annual international conference on VLSI design automation in Asia and South Pacific regions, one of the most active regions of design and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC.


2018 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of innovative research in all aspects of low power electronics and design, ranging from process technologies and analog/digital circuits, simulation and synthesis tools, system-level design and optimization, to system software and applications.



Periodicals related to Yield-enhancement Redundancy

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Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Dependable and Secure Computing, IEEE Transactions on

The purpose of TDSC is to publish papers in dependability and security, including the joint consideration of these issues and their interplay with system performance. These areas include but are not limited to: System Design: architecture for secure and fault-tolerant systems; trusted/survivable computing; intrusion and error tolerance, detection and recovery; fault- and intrusion-tolerant middleware; firewall and network technologies; system management ...


Design & Test of Computers, IEEE

IEEE Design & Test of Computers offers original works describing the methods used to design and test electronic product hardware and supportive software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. Topics include IC/module design, low-power design, electronic design automation, design/test verification, practical technology, and standards. IEEE Design & Test of ...



Most published Xplore authors for Yield-enhancement Redundancy

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Xplore Articles related to Yield-enhancement Redundancy

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New method of extraction of systematic failure component

2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203), 2001

We propose a novel model, which can describe systematic faults and is applicable to process improvement. In this model, the histogram of the faults is described as the sum of the Poisson distribution and the negative binomial distribution. The latter originates from the systematic failure component. By combining the analysis of the degree and the position of the systematic fault ...


State-of-the-art of the wafer scale ELSA project

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems, 1991

ELSA project concerns massively parallel architectures on silicon dedicated especially to low-level image processing. Real-time low-level image processing demands a huge amount of computing power. Fortunately, the algorithms encountered in this field are naturally regular which suggests a regular architecture to solve them. One of the most efficient scheme is array processors. This array processor has been implemented on a ...


Trading off area, yield and performance via hybrid redundancy in multi-core architectures

2013 IEEE 31st VLSI Test Symposium (VTS), 2013

Manufacturing yield is a major concern for modern CMOS technologies. Fortunately, evolving chip architectures such as multi-cores have provided new venues for yield enhancement, and calls for a fresh perspective on the classic method of redundancy insertion. In this paper we outline a new approach towards redundancy insertion in modern multi-core CPU architectures. Traditionally, applying redundancy at a finer intra-core ...


Memory Die Clustering and Matching for Optimal Voltage Window in Semiconductor

IEEE Transactions on Semiconductor Manufacturing, 2015

In this paper, we propose a method to optimize the product performance instantly by utilizing the internal voltage trimming circuit for Dynamic Random Access Memory (DRAM) memory. Specifically, we first define the verification wafer as the internal voltage characteristics using the clustering technique. Second, the optimized voltage conditions are applied to a normal wafer being matched with a verification wafer. ...


A self-correcting active pixel camera

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2000

Digital cameras on-a-chip are becoming more common and are expected to be used in many industrial and consumer products. With the size of the CMOS active pixel-array implemented in such chips increasing to 512/spl times/512 and beyond, the possibility of degradation in the reliability of the chip over time must be a factor in the chip design. In digital circuits, ...



Educational Resources on Yield-enhancement Redundancy

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IEEE-USA E-Books

  • New method of extraction of systematic failure component

    We propose a novel model, which can describe systematic faults and is applicable to process improvement. In this model, the histogram of the faults is described as the sum of the Poisson distribution and the negative binomial distribution. The latter originates from the systematic failure component. By combining the analysis of the degree and the position of the systematic fault with a lot history, the problem of the processes can be solved. In this way, it is possible to enhance yield and increase productivity.

  • State-of-the-art of the wafer scale ELSA project

    ELSA project concerns massively parallel architectures on silicon dedicated especially to low-level image processing. Real-time low-level image processing demands a huge amount of computing power. Fortunately, the algorithms encountered in this field are naturally regular which suggests a regular architecture to solve them. One of the most efficient scheme is array processors. This array processor has been implemented on a whole wafer instead of implementing it in VLSI chips each containing a few processing elements. Potential advantages of wafer scale integration over conventional VLSI systems include lower power, higher speed and small volume. However, WSI suffers from low yield. Redundancy and reconfiguration techniques are used to enhance the overall yield. Both of these have been implemented in ELSA. Three software packages have been developed to completely (re)configure the wafer and build a working target array.<<ETX>>

  • Trading off area, yield and performance via hybrid redundancy in multi-core architectures

    Manufacturing yield is a major concern for modern CMOS technologies. Fortunately, evolving chip architectures such as multi-cores have provided new venues for yield enhancement, and calls for a fresh perspective on the classic method of redundancy insertion. In this paper we outline a new approach towards redundancy insertion in modern multi-core CPU architectures. Traditionally, applying redundancy at a finer intra-core level of granularity provides great benefits in yield improvement, but requires additional steering logic and wiring that has a detrimental impact on area and performance. At the other end of the spectrum, coarse-grained core level redundancy can enable spare sharing, but it is only beneficial in highly-parallel GPU architectures. To this end, we will 1) introduce a hybrid spare sharing redundancy insertion scheme that combines the advantages of the above two approaches, while carefully leveraging the associated area and performance overheads, 2) present an extensively verified, systematic scalable model to evaluate the quality of the final design in terms of projected revenue per wafer, and 3) introduce a maximization algorithm to determine the near optimal redundancy configurations during the design stage. Experimental results show that our new design methodology provides more than 15% improvement in revenue per wafer, compared to using existing redundancy insertion techniques.

  • Memory Die Clustering and Matching for Optimal Voltage Window in Semiconductor

    In this paper, we propose a method to optimize the product performance instantly by utilizing the internal voltage trimming circuit for Dynamic Random Access Memory (DRAM) memory. Specifically, we first define the verification wafer as the internal voltage characteristics using the clustering technique. Second, the optimized voltage conditions are applied to a normal wafer being matched with a verification wafer. The proposed method makes the ability to apply a different voltage trimming condition for each dies internal voltage circuit depending on their characteristics, thereby improving the characteristics of the individual dies and reducing the fail bit count (FBC) further. The experimental results on the real-application case show that our proposed method reduces the FBC by 1%-5%, which contributes yield enhancement and quality improvement of DRAM memory by raising the efficiency of the redundancy cell repair in the repair process.

  • A self-correcting active pixel camera

    Digital cameras on-a-chip are becoming more common and are expected to be used in many industrial and consumer products. With the size of the CMOS active pixel-array implemented in such chips increasing to 512/spl times/512 and beyond, the possibility of degradation in the reliability of the chip over time must be a factor in the chip design. In digital circuits, a commonly used technique for reliability or yield enhancement is the incorporation of redundancy (e.g., adding redundant rows and columns in large memory ICs). Very limited attempts have been directed towards fault-tolerance in analog circuits, mainly due to the very high level of irregularity in their design. Since active pixel arrays have a regular structure, they are amenable to reliability enhancement through a limited amount of added redundancy. The purpose of this paper is to investigate the advantages of incorporating some fault-tolerance methods, including redundancy, into the design of an active pixel sensor array.



Standards related to Yield-enhancement Redundancy

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No standards are currently tagged "Yield-enhancement Redundancy"