Conferences related to Yield-enhancement Redundancy

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2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)

ASP-DAC 2018 is the 23rd annual international conference on VLSI design automation in Asia and South Pacific regions, one of the most active regions of design and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC.


2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)

The DATE conference addresses all aspects of research into technologies for electronic and embedded system engineering. It covers the design process, test, and automation tools for electronics ranging from integrated circuits to distributed embedded systems. This includes both hardware and embedded software design issues. The conference scope also includes the elaboration of design requirements and new architectures for challenging application fields such as telecoms, wireless communications, multimedia, healthcare, smart energy and automotive systems. Companies also present innovative industrial designs to foster the feedback fromrealworld design to research. DATE also hosts a number of special sessions, events within the main technical programme such as panels, hot-topic sessions, tutorials and workshops technical programme such as panels, hot-topic sessions, tutorials and workshops.

  • 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)

    The DATE conference addresses all aspects of research into technologies for electronic and embedded system engineering. It covers the design process, test, and automation tools for electronics ranging from integrated circuits to distributed embedded systems. This includes both hardware and embedded software design issues. The conference scope also includes the elaboration of design requirements and new architectures for challenging application fields such as telecoms, wireless communications, multimedia, healthcare, smart energy and automotive systems. Companies also present innovative industrial designs to foster the feedback fromrealworld design to research. DATE also hosts a number of special sessions, events within the main technical programme such as panels, hot-topic sessions, tutorials and workshops technical programme such as panels, hot-topic sessions, tutorials and workshops.

  • 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)

    The DATE conference addresses all aspects of research into technologies for electronic andembedded system engineering. It covers the design process, test, and automation tools forelectronics ranging from integrated circuits to distributed embedded systems. This includes bothhardware and embedded software design issues. The conference scope also includes theelaboration of design requirements and new architectures for challenging application fields suchas telecoms, wireless communications, multimedia, healthcare, smart energy and automotivesystems. Companies also present innovative industrial designs to foster the feedback from realworlddesign to research. DATE also hosts a number of special sessions, events within the maintechnical programme such as panels, hot-topic sessions, tutorials and workshops technical programme such as panels, hot-topic sessions, tutorials and workshops

  • 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)

    The DATE conference addresses all aspects of research into technologies for electronic and embedded system engineering. It covers the design process, test, and automation tools for electronics ranging from integrated circuits to distributed embedded systems. This includes both hardware and embedded software design issues. The conference scope also includes the elaboration of design requirements and new architectures for challenging application fields such as telecoms, wireless communications, multimedia, healthcare, smart energy and automotive systems. Companies also present innovative industrial designs to foster the feedback from realworld design to research. DATE also hosts a number of special sessions, events within the main technical programme such as panels, hot-topic sessions, tutorials and workshops.

  • 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)

    The DATE conference addresses all aspects of research into technologies for electronic and embedded system engineering. It covers the design process, test, and automation tools for electronics ranging from integrated circuits to distributed embedded systems. This includes both hardware and embedded software design issues. The conference scope also includes the elaboration of design requirements and new architectures for challenging application fields such as telecoms, wireless communications, multimedia, healthcare, smart energy and automotive systems. Companies also present innovative industrial designs to foster the feedback from real-world design to research. DATE also hosts a number of special sessions, events within the main technical programme such as panels, hot-topic sessions, tutorials and workshops

  • 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE 2013)

    DATE is the complete event for the European electronic and test community. A leading world conference and exhibition, DATE unites 2,000 professionals with approximately 60 exhibiting companies, cutting edge R&D, industrial designers and technical managers from around the world.

  • 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012)

    DATE is the complete event for the European electronic system and test community. A leading world conference and exhibition, DATE unites 2,000 professionals with some 60 exhibiting companies, cutting edge R&D, industrial designers and technical managers from around the world.

  • 2011 Design, Automation & Test in Europe Conference & Exhibition (DATE 2011)

    DATE is the complete event for the European electronic system and test community. A world leading conference and exhibition, DATE unites 2,000 professionals with some 60 exhibiting companies, cutting edge R&D, industrial designers and technical managers from around the world.

  • 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)

    All aspects of research into technologies for electronic and (embedded) systems engineering. It covers the design process, test, and tools for design automation of electronic products ranging from integrated circuits to distributed large-scale systems.

  • 2009 Design, Automation & Test in Europe Conference & Exhibition (DATE 2009)

    The Design, Automation, and Test in Europe (DATE) conference is the world's premier conference dedicated to electronics system design & test. The technical programme features: Four distinctive and integrated themes, covering all aspects of systems design and engineering. Two special days are focusing on SoC Development Strategies and Multicore Applications.

  • 2008 Design, Automation & Test in Europe Conference & Exhibition (DATE 2008)

    The 11th DATE conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. It puts strong emphasis on ICs/SoCs, reconfigurable hardware and embedded systems, including embedded software. The five-day event consists of a conference with plenary invited papers, regular papers, panels, hot-topic sessions, tutorials.

  • 2007 Design, Automation & Test in Europe Conference & Exhibition (DATE 2007)

    DATE is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. It puts strong emphasis on both ICs/SoCs, reconfigurable hardware and embedded systems, including embedded software.

  • 2006 Design, Automation & Test in Europe Conference & Exhibition (DATE 2006)

  • 2005 Design, Automation & Test in Europe Conference & Exhibition (DATE)

  • 2004 Design, Automation & Test in Europe Conference & Exhibition (DATE)

  • 2003 Design, Automation & Test in Europe Conference & Exhibition (DATE)

  • 2002 Design, Automation & Test in Europe Conference & Exhibition (DATE)

  • 2001 Design, Automation & Test in Europe Conference & Exhibition (DATE)

  • 2000 Design, Automation & Test in Europe Conference & Exhibition (DATE)

  • 1999 Design, Automation & Test in Europe Conference & Exhibition (DATE)


2018 IEEE European Test Symposium (ETS)

The scope of the conference is electronic-based circuits and system testing, including VLSI Test, VLSI Reliability, Yield, diagnosis, DFX, Verification, etc.


2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

ICCAD serves EDA and design professionals, highlighting new challenges and innovative solutions for integrated circuit design technology and systems


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Periodicals related to Yield-enhancement Redundancy

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Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


Computers, IEEE Transactions on

Design and analysis of algorithms, computer systems, and digital networks; methods for specifying, measuring, and modeling the performance of computers and computer systems; design of computer components, such as arithmetic units, data storage devices, and interface devices; design of reliable and testable digital devices and systems; computer networks and distributed computer systems; new computer organizations and architectures; applications of VLSI ...


Dependable and Secure Computing, IEEE Transactions on

The purpose of TDSC is to publish papers in dependability and security, including the joint consideration of these issues and their interplay with system performance. These areas include but are not limited to: System Design: architecture for secure and fault-tolerant systems; trusted/survivable computing; intrusion and error tolerance, detection and recovery; fault- and intrusion-tolerant middleware; firewall and network technologies; system management ...


Design & Test of Computers, IEEE

IEEE Design & Test of Computers offers original works describing the methods used to design and test electronic product hardware and supportive software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. Topics include IC/module design, low-power design, electronic design automation, design/test verification, practical technology, and standards. IEEE Design & Test of ...


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Most published Xplore authors for Yield-enhancement Redundancy

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Xplore Articles related to Yield-enhancement Redundancy

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New method of extraction of systematic failure component

2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203), 2001

We propose a novel model, which can describe systematic faults and is applicable to process improvement. In this model, the histogram of the faults is described as the sum of the Poisson distribution and the negative binomial distribution. The latter originates from the systematic failure component. By combining the analysis of the degree and the position of the systematic fault ...


State-of-the-art of the wafer scale ELSA project

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems, 1991

ELSA project concerns massively parallel architectures on silicon dedicated especially to low-level image processing. Real-time low-level image processing demands a huge amount of computing power. Fortunately, the algorithms encountered in this field are naturally regular which suggests a regular architecture to solve them. One of the most efficient scheme is array processors. This array processor has been implemented on a ...


Trading off area, yield and performance via hybrid redundancy in multi-core architectures

2013 IEEE 31st VLSI Test Symposium (VTS), 2013

Manufacturing yield is a major concern for modern CMOS technologies. Fortunately, evolving chip architectures such as multi-cores have provided new venues for yield enhancement, and calls for a fresh perspective on the classic method of redundancy insertion. In this paper we outline a new approach towards redundancy insertion in modern multi-core CPU architectures. Traditionally, applying redundancy at a finer intra-core ...


Memory Die Clustering and Matching for Optimal Voltage Window in Semiconductor

IEEE Transactions on Semiconductor Manufacturing, 2015

In this paper, we propose a method to optimize the product performance instantly by utilizing the internal voltage trimming circuit for Dynamic Random Access Memory (DRAM) memory. Specifically, we first define the verification wafer as the internal voltage characteristics using the clustering technique. Second, the optimized voltage conditions are applied to a normal wafer being matched with a verification wafer. ...


A self-correcting active pixel camera

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2000

Digital cameras on-a-chip are becoming more common and are expected to be used in many industrial and consumer products. With the size of the CMOS active pixel-array implemented in such chips increasing to 512/spl times/512 and beyond, the possibility of degradation in the reliability of the chip over time must be a factor in the chip design. In digital circuits, ...



Educational Resources on Yield-enhancement Redundancy

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IEEE.tv Videos

IMS 2012 Microapps - Improve Microwave Circuit Design Flow Through Passive Model Yield and Sensitivity Analysis
IMS 2011 Microapps - Yield Analysis During EM Simulation
IMS 2011 Microapps - Improved Microwave Device Characterization and Qualification Using Affordable Microwave Microprobing Techniques for High-Yield Production of Microwave Components
Five Questions for Inventor Dean Kamen
Data and Algorithmic Bias in the Web - Ricardo Baeza-Yates - WCCI 2016
Micro-Apps 2013: How to Make Your Designs More Robust
Design of Monolithic Silicon-Based Envelope-Tracking Power Amplifiers for Broadband Wireless Applications
GHTC 2012 Gertjan van Stam Keynote
A High-Efficiency Linear Power Amplifier for 28GHz Mobile Communications in 40nm CMOS: RFIC Interactive Forum 2017
Active Space-Body Perception and Body Enhancement using Dynamical Neural Systems
High-Bandwidth Memory Interface Design
"ITRS 2.0 and Its System Drivers: Focus on Systems Trends and 'MTM' (Rebooting Computing)
Intermodulation Distortion Mitigation in Microwave Amplifiers and Frequency Converters
CIRCUIT DESIGN USING FINFETS
IEEE Green Energy Summit 2015, Panel 2: How reliable is reliable enough?
When Do We Resort to EC in the Communications Industry, and What is Needed in the Future? - IEEE Congress on Evolutionary Computation 2017
The Future of Innovation and the Creation of Knowledge in a Post-Internet World: Joi Ito, MIT Media Lab
A perspective shift from Fuzzy logic to Neutrosophic Logic - Swati Aggarwal
Micro-Apps 2013: Frequency Planning Synthesis for Wireless Systems Design
Flywheel Energy Storage for the 21st Century: APEC 2019

IEEE-USA E-Books

  • New method of extraction of systematic failure component

    We propose a novel model, which can describe systematic faults and is applicable to process improvement. In this model, the histogram of the faults is described as the sum of the Poisson distribution and the negative binomial distribution. The latter originates from the systematic failure component. By combining the analysis of the degree and the position of the systematic fault with a lot history, the problem of the processes can be solved. In this way, it is possible to enhance yield and increase productivity.

  • State-of-the-art of the wafer scale ELSA project

    ELSA project concerns massively parallel architectures on silicon dedicated especially to low-level image processing. Real-time low-level image processing demands a huge amount of computing power. Fortunately, the algorithms encountered in this field are naturally regular which suggests a regular architecture to solve them. One of the most efficient scheme is array processors. This array processor has been implemented on a whole wafer instead of implementing it in VLSI chips each containing a few processing elements. Potential advantages of wafer scale integration over conventional VLSI systems include lower power, higher speed and small volume. However, WSI suffers from low yield. Redundancy and reconfiguration techniques are used to enhance the overall yield. Both of these have been implemented in ELSA. Three software packages have been developed to completely (re)configure the wafer and build a working target array.<<ETX>>

  • Trading off area, yield and performance via hybrid redundancy in multi-core architectures

    Manufacturing yield is a major concern for modern CMOS technologies. Fortunately, evolving chip architectures such as multi-cores have provided new venues for yield enhancement, and calls for a fresh perspective on the classic method of redundancy insertion. In this paper we outline a new approach towards redundancy insertion in modern multi-core CPU architectures. Traditionally, applying redundancy at a finer intra-core level of granularity provides great benefits in yield improvement, but requires additional steering logic and wiring that has a detrimental impact on area and performance. At the other end of the spectrum, coarse-grained core level redundancy can enable spare sharing, but it is only beneficial in highly-parallel GPU architectures. To this end, we will 1) introduce a hybrid spare sharing redundancy insertion scheme that combines the advantages of the above two approaches, while carefully leveraging the associated area and performance overheads, 2) present an extensively verified, systematic scalable model to evaluate the quality of the final design in terms of projected revenue per wafer, and 3) introduce a maximization algorithm to determine the near optimal redundancy configurations during the design stage. Experimental results show that our new design methodology provides more than 15% improvement in revenue per wafer, compared to using existing redundancy insertion techniques.

  • Memory Die Clustering and Matching for Optimal Voltage Window in Semiconductor

    In this paper, we propose a method to optimize the product performance instantly by utilizing the internal voltage trimming circuit for Dynamic Random Access Memory (DRAM) memory. Specifically, we first define the verification wafer as the internal voltage characteristics using the clustering technique. Second, the optimized voltage conditions are applied to a normal wafer being matched with a verification wafer. The proposed method makes the ability to apply a different voltage trimming condition for each dies internal voltage circuit depending on their characteristics, thereby improving the characteristics of the individual dies and reducing the fail bit count (FBC) further. The experimental results on the real-application case show that our proposed method reduces the FBC by 1%-5%, which contributes yield enhancement and quality improvement of DRAM memory by raising the efficiency of the redundancy cell repair in the repair process.

  • A self-correcting active pixel camera

    Digital cameras on-a-chip are becoming more common and are expected to be used in many industrial and consumer products. With the size of the CMOS active pixel-array implemented in such chips increasing to 512/spl times/512 and beyond, the possibility of degradation in the reliability of the chip over time must be a factor in the chip design. In digital circuits, a commonly used technique for reliability or yield enhancement is the incorporation of redundancy (e.g., adding redundant rows and columns in large memory ICs). Very limited attempts have been directed towards fault-tolerance in analog circuits, mainly due to the very high level of irregularity in their design. Since active pixel arrays have a regular structure, they are amenable to reliability enhancement through a limited amount of added redundancy. The purpose of this paper is to investigate the advantages of incorporating some fault-tolerance methods, including redundancy, into the design of an active pixel sensor array.



Standards related to Yield-enhancement Redundancy

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Jobs related to Yield-enhancement Redundancy

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