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The conference program will consist of plenary lectures, symposia, workshops and invitedsessions of the latest significant findings and developments in all the major fields of biomedical engineering.Submitted full papers will be peer reviewed. Accepted high quality papers will be presented in oral and poster sessions,will appear in the Conference Proceedings and will be indexed in PubMed/MEDLINE.
2021 IEEE Photovoltaic Specialists Conference (PVSC)
Photovoltaic materials, devices, systems and related science and technology
Energy conversion and conditioning technologies, power electronics, adjustable speed drives and their applications, power electronics for smarter grid, energy efficiency,technologies for sustainable energy systems, converters and power supplies
The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.
The Annual IEEE PES General Meeting will bring together over 2900 attendees for technical sessions, administrative sessions, super sessions, poster sessions, student programs, awards ceremonies, committee meetings, tutorials and more
Experimental and theoretical advances in antennas including design and development, and in the propagation of electromagnetic waves including scattering, diffraction and interaction with continuous media; and applications pertinent to antennas and propagation, such as remote sensing, applied optics, and millimeter and submillimeter wave techniques.
Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission
The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...
Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.
Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2018
As designs continue to grow in size and complexity, EDA paradigm shifts from flat to hierarchical timing analysis. In this paper, we discuss timing macro modeling, which is the key to enable efficient and accurate hierarchical timing analysis. We briefly review conventional models and recent research progresses in timing macro modeling. We try to answer the following questions: How can ...
IEE Proceedings - Circuits, Devices and Systems, 2003
A new timing recovery circuit for high-speed optical storage drives is presented. The core of the timing recovery circuit is a mixed-signal- controlled oscillator (MSCO) which is controlled simultaneously by a digital signal and an analogue signal. With digital control, the MSCO can operate in a broad frequency range, with very high switching speed and flexibility. Within a small frequency ...
2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2018
This paper describes low latency bimodal NRZ/ PAM-4 timing recovery. This scheme reduces latency and power consumption by eliminating the need for data equalization in the timing recovery path for inter-symbol-interference limited channels. Rather it directly equalizes the data dependent jitter by adaptively shifting the ISI effected zero crossings. The implemented prototype in 65nm CMOS supports both 10 Gb/s NRZ ...
2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 2018
As design complexity rapidly grows, a modem design contains more complex constraints and has more clock domains. To these stringent timing requirements, a design is iteratively optimized. Along with intensive optimizations, fast timing analysis guiding designers to fix timing violations is desired. Thus far, previous works have focused on either timing exception handling or path search only. Different from them, ...
2008 Eighth International Conference on Hybrid Intelligent Systems, 2008
To solve the problem of fluctuations in clock timing with digital LSIs (also known as the "clock skew" problem), we propose a genetic algorithm (GA) based clock adjustment method that ensures robust clock-timing to cope with fluctuations in the LSI environment such as temperature or power supply voltage. This method is realized by the combination of dedicated adjustable circuitry and ...
ON-CHIP VOLTAGE AND TIMING DIAGNOSTIC CIRCUITS
Spike Timing, Rhythms, and the Effective Use of Neural Hardware
Evolution of Optical and Transport Technologies for 5G Crosshaul Networks - IEEE Future Networks Initiative webinar
Spiking Network Algorithms for Scientific Computing - William Severa: 2016 International Conference on Rebooting Computing
Accelerating Discrete Fourier Transforms with Dot-product engine - Miao Hu: 2016 International Conference on Rebooting Computing
Micro-Apps 2013: Environment Simulation for Counter-IED Jammer Test
Hyperdimensional Biosignal Processing: A Case Study for EMG-based Hand Gesture Recognition - Abbas Rahimi: 2016 International Conference on Rebooting Computing
Accelerating Machine Learning with Non-Volatile Memory: Exploring device and circuit tradeoffs - Pritish Narayanan: 2016 International Conference on Rebooting Computing
Kurt Petersen: 2019 IEEE Medal of Honor Recipient
As designs continue to grow in size and complexity, EDA paradigm shifts from flat to hierarchical timing analysis. In this paper, we discuss timing macro modeling, which is the key to enable efficient and accurate hierarchical timing analysis. We briefly review conventional models and recent research progresses in timing macro modeling. We try to answer the following questions: How can timing macro models be made compact and accurate? How do state-of-the art works maintain model accuracy, model size, model generation performance, and model usage performance? Finally, future research directions on timing macro modeling are identified.
A new timing recovery circuit for high-speed optical storage drives is presented. The core of the timing recovery circuit is a mixed-signal- controlled oscillator (MSCO) which is controlled simultaneously by a digital signal and an analogue signal. With digital control, the MSCO can operate in a broad frequency range, with very high switching speed and flexibility. Within a small frequency step defined by a particular digital control word, an analogue control signal can then fine-tune the MSCO through a feedback loop. In addition, to accommodate the data-transition characteristics in the CD-ROM or DVD-ROM data, a new phase detector is proposed. The proposed IC also includes a frame synchronisation block and an eight-to-fourteen demodulation circuit for CD-ROM data recovery. The chip was fabricated in a 0.6-/spl mu/m n-well SPTM CMOS process. The timing recovery circuit achieves an operating frequency range of 70-180 MHz and its acquisition time is much less than 1 /spl mu/s while consuming only 85 mW from a 5 V power supply
This paper describes low latency bimodal NRZ/ PAM-4 timing recovery. This scheme reduces latency and power consumption by eliminating the need for data equalization in the timing recovery path for inter-symbol-interference limited channels. Rather it directly equalizes the data dependent jitter by adaptively shifting the ISI effected zero crossings. The implemented prototype in 65nm CMOS supports both 10 Gb/s NRZ and 20 Gb/s PAM-4 consuming only 23 mW. The CDR achieves more than fbaud/500 peaking free tracking bandwidth and adapts to optimized jitter tolerance for both PAM-4 and NRZ for the given input eye.
As design complexity rapidly grows, a modem design contains more complex constraints and has more clock domains. To these stringent timing requirements, a design is iteratively optimized. Along with intensive optimizations, fast timing analysis guiding designers to fix timing violations is desired. Thus far, previous works have focused on either timing exception handling or path search only. Different from them, in this paper, we tackle these two issues together for the urgent need in modern design. We first generalize timing exceptions to model all common timing exceptions and other path-specific timing quantities. Then, we propose a novel timing analysis flow that performs fast path search for generalized timing exception handling. Furthermore, we develop three delicate techniques to achieve fast path search, including local slack bounds, dynamic slack recovering, and slack priority queue. Experimental results show that our model is general, and our flow is promising with high efficiency and scalability.
To solve the problem of fluctuations in clock timing with digital LSIs (also known as the "clock skew" problem), we propose a genetic algorithm (GA) based clock adjustment method that ensures robust clock-timing to cope with fluctuations in the LSI environment such as temperature or power supply voltage. This method is realized by the combination of dedicated adjustable circuitry and adjustment GA software, with the values for multiple adjustable delay circuits inserted into the clock lines being determined by the GA software after fabrication. Experimental results demonstrate that the proposed method can enhance the operational yields of developed test chips while ensuring sufficient timing margins.
The DIII-D Tokamak relies on a facility wide timing network to synchronize machine operations. The first generation system was designed around cascaded CAMAC delay units feeding a custom timing network encoder. This system has become increasingly difficult to maintain and repair and the needs of DIII-D experiments are beginning to exceed its capabilities. To address these issues, a new second-generation system was designed with a modular architecture in a VME form factor that facilitates the future addition of features and output channels when required, while maintaining backwards compatibility with the original system. As part of the base design, modules for event triggers, multiple programmable sequences, first generation Bi-Phase serial outputs, fiber optic outputs, and event recording are provided. Each module is implemented with a form of programmable logic, either a CPLD or FPGA, which allows for future modification if needed. The system also has the capability of complete remote management, allowing for custom timing chains on a per- experiment basis. The feature set and design of this second-generation timing system is presented.
To reduce the risk of costly timing errors detected after the integration phase, there is a need for efficient, reliable and automated timing prediction methods applicable already at the early design stages, even if based on incomplete or partial timing information. The obtained timing estimations can be consolidated along the different design phases, until the final integration. Model-Checking is a good candidate for coarse grained timing verification, since, for such use, it does scale and provide exact estimates. However, its use in the industry is conditioned by a seamless integration in the development process. In this paper, we present our solution to connect the model-checking tool ROMEO to the design process, thus allowing the verification of the system timing behavior at early stages.
New results about the pre-filter and the post-filter in timing recovery based on square-law detection are presented. Specifically, in the paper a matched- filter-type condition that guarantees optimality of the pre-filter against channel noise is derived. This condition can be satisfied together with the known condition for self-noise elimination, thus achieving optimality against self-noise and against channel noise simultaneously. The post-filter is optimized by introducing a phase noise model for the phase of the timing wave used at the transmit side for generating the data signal. The case of random phase walk is analyzed in detail, and, having optimized both the pre-filter and the post-filter, we conclude that the minimum variance of the normalized timing error for a given spectral quality of the source timing wave and for a given channel signal-to-noise ratio goes with (alphaT)<sup>-0.5</sup>, where T is the symbol repetition interval and alpha is the roll-off factor.
This paper describes a study of power-supply noise and substrate noise impact on the timing properties of two nonoverlapping clock generation circuits that are typically used in sigma-delta modulators. The constituent logic blocks of the clock generation circuits are also individually characterized where special attention has been put on the inverter whose behavior is fully described in mathematical terms. The analytical model is verified with SPICE using 0.35-mum CMOS process parameters, and a reference simulation in 0.18 mum is also presented showing the trend of technology downscaling. Furthermore, the nonoverlapping clock generation circuits are characterized in the 0.18-mum process and the phenomenon of jitter peaking is described. Finally, all variations of connection configurations in the clock generation circuits are explored to reveal possible optimal configurations.
Traditional processor design incorporates voltage and frequency guardbands to ensure correct execution of operations under worst-case conditions. As transistor density increases and manufacturing processes improve, increasingly costly guardbands are required to deal with the impacts of environmental variability. The use of timing speculation can relax the tight constraint for worst-case design by allowing occasional errors, which are detected and corrected later by an error resilience mechanism. However, a program's performance may suffer owing to timing errors. This paper analyzes program behaviors and proposes a loop transformation technique for timing speculative architectures. We observe relationships between program behaviors and timing errors through a simulator. From the analytical results, a loop transformation technique is developed to reduce timing errors. It is implemented and evaluated using LLVM compiler infrastructure. For the tested benchmark programs, the proposed loop transformation can reduce timing error counts by up to 37%.