Testability

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Testability, a property applying to an empirical hypothesis, involves two components: (1) the logical property that is variously described as contingency, defeasibility, or falsifiability, which means that counterexamples to the hypothesis are logically possible, and (2) the practical feasibility of observing a reproducible series of such counterexamples if they do exist. (Wikipedia.org)






Conferences related to Testability

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2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

ECTC is the premier international conference sponsored by the IEEE Components, Packaging and Manufacturing Society. ECTC paper comprise a wide spectrum of topics, including 3D packaging, electronic components, materials, assembly, interconnections, device and system packaging, optoelectronics, reliability, and simulation.


2019 20th International Symposium on Quality Electronic Design (ISQED)

20th International Symposium on Quality Electronic Design (ISQED 2019) is the premier interdisciplinary and multidisciplinary Electronic Design conference?bridges the gap among Electronic/Semiconductor ecosystem members providing electronic design tools, integrated circuit technologies, semiconductor technology,packaging, assembly & test to achieve design quality.


2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)

This conference is a forum for researchers and designers to present and discuss variousaspects of VLSI design, EDA, embedded systems, and enabling technologies. The program willconsist of regular paper sessions, special sessions, embedded tutorials, panel discussions,design contest, industrial exhibits and tutorials. This is the premier conference/exhibition in thisarea in India, attracting designers, EDA professionals, and EDA tool users. The programcommittee for the conference has a significant representation from the EDA researchcommunity and a large fraction of the papers published in this conference are EDA-related


2019 IEEE 37th VLSI Test Symposium (VTS)

This premier IEEE Symposium will bring together scientists, academics, and practicing engineers from all over the world to explore emerging trends and novel concepts in testing, and verification & validation of microelectronic circuits and systems. The aim of this conference is to provide an international forum for these experts to promote, share, and discuss various issues and developments in the growing field of VLSI Test.


2019 IEEE 9th Symposium on Computer Applications & Industrial Electronics (ISCAIE)

Industrial Electronics, Computational Intelligence, Information Engineering, Network & Communication Technologies,Signal & Image Processing, Trusted Computing & Secure Systems, Software Engineering, Internet of Things


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Periodicals related to Testability

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Aerospace and Electronic Systems Magazine, IEEE

The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.


Automatic Control, IEEE Transactions on

The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Communications Magazine, IEEE

IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...


Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities. Practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.


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Most published Xplore authors for Testability

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Xplore Articles related to Testability

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Design and code time testability analysis for object oriented systems

2014 International Conference on Computing for Sustainable Global Development (INDIACom), 2014

In last few decades object oriented software design approach is widely chosen by programmers to design any large and complex system. As the complexity of object oriented software increases, design for testability becomes a necessary task for these systems. The performance of testability is also directly affected by software design for testability. Therefore to make the task of testability more ...


Design for testability reuse in synthesis for testability

Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387), 1999

This paper presents our Design for Testability reuse approach implemented in the allocation for testability system IDAT. In the context of High-Level Synthesis for Testability, the allocation for testability process mainly consists in searching for the best cost/quality trade-off between the designer requirements and testability means which can be proposed by the system, considering the available components in the library ...


Testability aspects of a DSP based image processing system

IEE Colloquium on Systems Design for Testability, 1995

The Coherent and Electro-Optics Research Group at Liverpool John Moores University has designed and developed several desktop imaging systems for industrial and medical applications. In 1991 a system based on a TMS320C30 DSP circuit board was produced to perform image correlation tasks. The board eventually demonstrated the power of the 'C30, but it also highlighted the need for new test ...


Testability preserving and enhancing transformations for robust delay fault testability

Proceedings Eleventh International Conference on VLSI Design, 1998

Multilevel logic optimization transformations for DFT (design for testability) used in existing logic systems, are characterized with respect to their testability preserving and testability enhancing properties. In this paper, we propose three new transformations which preserve or improve path delay testability with reduction in circuitry. The paper also includes a theorem showing the condition under which a testability preserving transformation ...


Bayesian networks based testability prediction of electronic equipment

IEEE 2011 10th International Conference on Electronic Measurement & Instruments, 2011

The complexity of modern electronic equipment is putting new demand on system testability. Well design for testability (DFT) can save cost in fault detection and isolation, promote efficiency of system maintenance. The primary goal of testability prediction is to analyze and evaluate testability figures of merit (TFOMs) of unit under test (UUT) to support the assessment of the quality of ...


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Educational Resources on Testability

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IEEE.tv Videos

No IEEE.tv Videos are currently tagged "Testability"

IEEE-USA E-Books

  • Design and code time testability analysis for object oriented systems

    In last few decades object oriented software design approach is widely chosen by programmers to design any large and complex system. As the complexity of object oriented software increases, design for testability becomes a necessary task for these systems. The performance of testability is also directly affected by software design for testability. Therefore to make the task of testability more effective, smooth, and reliable, we need the concept of design for testability. Design for testability can be applied during the design time as well as code time but both have its own concerns. This paper discusses design for testability analysis to enhance the testability of object oriented systems.

  • Design for testability reuse in synthesis for testability

    This paper presents our Design for Testability reuse approach implemented in the allocation for testability system IDAT. In the context of High-Level Synthesis for Testability, the allocation for testability process mainly consists in searching for the best cost/quality trade-off between the designer requirements and testability means which can be proposed by the system, considering the available components in the library and the possibility of generating additional testability structures. The cost/quality trade-off is also based on the result of the testability analysis process.

  • Testability aspects of a DSP based image processing system

    The Coherent and Electro-Optics Research Group at Liverpool John Moores University has designed and developed several desktop imaging systems for industrial and medical applications. In 1991 a system based on a TMS320C30 DSP circuit board was produced to perform image correlation tasks. The board eventually demonstrated the power of the 'C30, but it also highlighted the need for new test protocols when commissioning boards with high density PGA and surface mount components. Since 1992 the group has been developing a new board based on the next generation TMS320C40 DSP. In order to minimise foreseeable development problems, the board has been designed for test using implementations of the IEE1149.1 boundary scan standard. This paper describes the imaging system, the processor board and the testability aspects associated with its development.

  • Testability preserving and enhancing transformations for robust delay fault testability

    Multilevel logic optimization transformations for DFT (design for testability) used in existing logic systems, are characterized with respect to their testability preserving and testability enhancing properties. In this paper, we propose three new transformations which preserve or improve path delay testability with reduction in circuitry. The paper also includes a theorem showing the condition under which a testability preserving transformation (TPT) will be a testability enhancing transformations (TET).

  • Bayesian networks based testability prediction of electronic equipment

    The complexity of modern electronic equipment is putting new demand on system testability. Well design for testability (DFT) can save cost in fault detection and isolation, promote efficiency of system maintenance. The primary goal of testability prediction is to analyze and evaluate testability figures of merit (TFOMs) of unit under test (UUT) to support the assessment of the quality of DFT. Bayesian networks (BNs) are the combination of probability theory and graph theory, which has exhibited distinguished performance in representation and reasoning of uncertainty knowledge. So we combine BNs and testability prediction project together. The testability prediction method based on BNs can not only be modeled conveniently, and easy to be integrated into information framework of testability engineering. Predicted result from Bayesian method is more believable than traditional methods.

  • Design for Testability

    None

  • The concepts, methods and technics for the electronic testability implementation

    The first part of the paper briefly describes the necessity of testability and the design-for-test concept. The testability problem is presented at the integrated circuit, printed circuit board layout and electronics module levels. In the second part, several very important strategies for testability development are proposed (in nine stages). As applications, testing practice problems are presented, including testing of printed circuit board and link connections (connection interrupts or unsoldered connections, short-circuit to GND), and testing of circuit board connectors (connector with broken or bent pin, network terminator fault, conflict on the network). The final part of the paper presents a system for verification of component positioning on the board by image acquisition and processing (orientation, correct value and type of component, correct solders).

  • A testability growth model based on evidential reasoning with nonlinear optimization

    Testability growth is a process that aims to improve the testability level of the equipment via identifying and removing the testability design defects (TDDs). The establishment of the existing testability growth model (TGM) needs to consider a variety of factors, it's difficult to describe it accurately. To solve this problem, a TGM based on evidential reasoning (ER) method with nonlinear optimization is studied in this paper. According to the growth test data that can achieve the testability growth tracking and predicting. To estimate the parameters of the TGM accurately by using the mean square error (MSE). Finally, growth test data of a stable tracking platform is used to verify the validity of the model. The results show that the tracking accuracy is in the order of 0.0013 magnitude.

  • An applicable testability framework for small satellite under the operational response space

    Focused on the significant features such as highly integration, flexible assembly and rapid testability of small satellite under the operational response space (SSUORS), an applicable framework of design for testability (DFT) is proposed to assure the testability of the SSUORS system. A combined structure of the DFT framework is presented to assure the system-level testability. Further, three patterns of extended build-in test are proposed to enhance the function-level testability, which are specified as additional testability requirements. In addition, both simple and complex scenario-based assignment test models are established based on the proposed DFT framework respectively. Compared with the traditional DFT, more complicated test requirements can be realized sufficiently, and more flexible test strategies can be implemented conveniently by the proposed DFT framework.

  • A low overhead design for testability and test generation technique for core-based systems-on-a-chip

    In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has several advantages in terms of time-to-market and system cost, testing such core-based systems is difficult, mainly due to the problem of justifying test sequences at the inputs of a core embedded deep in the circuit and propagating test responses from the core outputs. In this paper, we first present a design for testability technique for testing such core-based systems. In this scheme, untestable cores are first made testable using hierarchical testability analysis techniques. If necessary, additional testability hardware is added to the cores to make them transparent so that they can propagate test data without information loss. This testability and transparency technique is currently applicable to cores of the following types: application-specific integrated circuits, application-specific programmable processors, and application-specific instruction processors. Other core types can be made testable and transparent using traditional techniques. The testable and transparent cores can then he integrated together with some system-level testability hardware to ensure justification of precomputed test sequences of each core from system primary inputs to the core inputs and propagation of test responses from core outputs to system primary outputs. Justification and propagation of test sequences are done at the system level by extending and suitably modifying the symbolic hierarchical testability analysis method that has been successfully applied to register- transfer level circuits. Since the testability analysis method is symbolic, the system test generation method is independent of the bit-width of the cores. The system-level test set is obtained as a byproduct of the testability analysis and insertion method without further search. The test methodology was applied to six example systems. Besides the proposed test method, the two methods that are currently used in the industry were also evaluated: (1) FScan-BScan, where each core is full-scanned, and system test is performed using boundary scan and (2) FScan-TBus, where each core is full-scanned, and system test is performed using a test bus. The experiments show that the proposed scheme has significantly lower area overhead, delay overhead, and test application time compared to FScan-BScan and FScan-TBus, without any compromise in the system fault coverage.



Standards related to Testability

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IEEE Standard for Testability and Diagnosability Characteristics and Metrics

This standard defines technology independent testability and diagnosability characteristics and metrics, particularly those based on relevant standard information models including standard AI-ESTATE (IEEE 1232.1 and P1232.3) information models.


Systems and software engineering -- Software life cycle processes

This International Standard establishes a common framework for software life cycle processes, with welldefined terminology, that can be referenced by the software industry. It contains processes, activities, and tasks that are to be applied during the acquisition of a software product or service and during the supply, development, operation, maintenance and disposal of software products. Software includes the software portion ...