Conferences related to System-on-chip

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2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe)

Energy conversion and conditioning technologies, power electronics, adjustable speed drives and their applications, power electronics for smarter grid, energy efficiency,technologies for sustainable energy systems, converters and power supplies


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE Applied Power Electronics Conference and Exposition (APEC)

APEC focuses on the practical and applied aspects of the power electronics business. Not just a power designer’s conference, APEC has something of interest for anyone involved in power electronics including:- Equipment OEMs that use power supplies and converters in their equipment- Designers of power supplies, dc-dc converters, motor drives, uninterruptable power supplies, inverters and any other power electronic circuits, equipments and systems- Manufacturers and suppliers of components and assemblies used in power electronics- Manufacturing, quality and test engineers involved with power electronics equipment- Marketing, sales and anyone involved in the business of power electronic- Compliance engineers testing and qualifying power electronics equipment or equipment that uses power electronics


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


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Periodicals related to System-on-chip

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Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Communications Magazine, IEEE

IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...


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Xplore Articles related to System-on-chip

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60 GHz system-on-chip (SoC) with built-in memory and an on-chip antenna

The 8th European Conference on Antennas and Propagation (EuCAP 2014), 2014

A novel 60 GHz transmitter SoC with an on-chip antenna and integrated memory in CMOS 65 nm technology is presented in this paper. This highly integrated transmitter design can support a data rate of 2 GBPS with a transmission range of 1 m. The transmitter consists of a fundamental frequency 60 GHz PLL which covers the complete ISM band. The ...


Performance evaluation of virtual channel flow control in centralized and distributed networks for system on chip

2017 29th International Conference on Microelectronics (ICM), 2017

On-chip communication is one of the main challenges introduced to high level integrated system-on-chip design. To address complexity and wiring challenges, network-on-chip has been proposed as a prominent solution capable of providing a reliable and efficient communication platform. Accordingly, network design counts as a key parameter that defines the overall system performance. In this paper, we propose a network design ...


T4A: System-on-chip design using Tri-gate technology

2014 27th IEEE International System-on-Chip Conference (SOCC), 2014

At the cutting edge of silicon IC technology we have seen a move from the planar processes used for the last 50 years, to a new three dimensional approach to device design. State of the art production silicon at the 20nm process node uses silicon Tri-gate devices, and it is expected this will continue at the 14-16nm process geometry nodes. ...


System-on-Chip implementation of Reliable Ethernet Networks nodes

IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society, 2013

Reliable Ethernet Networks are gaining acceptance for many Industrial Automation applications. However, the diversity and variety of emerging Ethernet based Industrial Protocols make difficult for the Industry the selection of the technology to implement them. Furthermore, the continue evolution of the standards and their combination increment the risk in the engineering decisions. This need for flexibility combined with the need ...


Miniaturized 122 GHz system-on-chip radar sensor with on-chip antennas utilizing a novel antenna design approach

2016 IEEE MTT-S International Microwave Symposium (IMS), 2016

This paper describes a highly-integrated 122 GHz system-on-chip radar sensor in a SiGe BiCMOS technology. The chip includes a radar transceiver and two on- chip antennas utilizing a novel antenna design approach that allows the use of the localized backside etching technique without compromising the mechanical stability of the chip. The implemented double folded dipole antenna achieves an antenna gain ...


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Educational Resources on System-on-chip

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IEEE-USA E-Books

  • 60 GHz system-on-chip (SoC) with built-in memory and an on-chip antenna

    A novel 60 GHz transmitter SoC with an on-chip antenna and integrated memory in CMOS 65 nm technology is presented in this paper. This highly integrated transmitter design can support a data rate of 2 GBPS with a transmission range of 1 m. The transmitter consists of a fundamental frequency 60 GHz PLL which covers the complete ISM band. The modulator following the PLL can support both BPSK and OOK modulation schemes. Both stored data on the integrated memory or directly from an external source can be transmitted. A tapered slot on chip antenna is integrated with the power amplifier to complete the front end of the transmitter design. Size of the complete transmitter with on-chip antenna is only 1.96 mm × 1.96 mm. The core circuits consume less than 100 mW of power. The high data rate capability of the design makes it extremely suitable for bandwidth hungry applications such as unencrypted HD video streaming and transmission.

  • Performance evaluation of virtual channel flow control in centralized and distributed networks for system on chip

    On-chip communication is one of the main challenges introduced to high level integrated system-on-chip design. To address complexity and wiring challenges, network-on-chip has been proposed as a prominent solution capable of providing a reliable and efficient communication platform. Accordingly, network design counts as a key parameter that defines the overall system performance. In this paper, we propose a network design that integrates centralized routers in distributed networks. Our results are compared to distributed networks of different sizes using a variety of synthetic traffic patterns and benchmarks.

  • T4A: System-on-chip design using Tri-gate technology

    At the cutting edge of silicon IC technology we have seen a move from the planar processes used for the last 50 years, to a new three dimensional approach to device design. State of the art production silicon at the 20nm process node uses silicon Tri-gate devices, and it is expected this will continue at the 14-16nm process geometry nodes. It is thus important to understand the specific design issues associated with system on chip circuit design using Tri-gate technology. This tutorial analyzes the design risks and benefits of using bulk tri-gate compared to conventional planar processes.

  • System-on-Chip implementation of Reliable Ethernet Networks nodes

    Reliable Ethernet Networks are gaining acceptance for many Industrial Automation applications. However, the diversity and variety of emerging Ethernet based Industrial Protocols make difficult for the Industry the selection of the technology to implement them. Furthermore, the continue evolution of the standards and their combination increment the risk in the engineering decisions. This need for flexibility combined with the need for hardware processing make FPGAs and reconfigurable devices in general, the best candidates to implement network devices and equipments able to deal with these issues. In this work, 3 architectures for Reliable Network Devices that support HSR and PRP protocols are presented. These architectures benefit from cutting-edge 28nm silicon fabrication reconfigurable technology combined with on-chip ARM processors and peripheral. One of the proposed architectures is implemented following a Design Flow that integrates 3 complex EDA tools and a third-party IP to achieve a full operative Reliable Networking Device with HSR and PRP processing capabilities.

  • Miniaturized 122 GHz system-on-chip radar sensor with on-chip antennas utilizing a novel antenna design approach

    This paper describes a highly-integrated 122 GHz system-on-chip radar sensor in a SiGe BiCMOS technology. The chip includes a radar transceiver and two on- chip antennas utilizing a novel antenna design approach that allows the use of the localized backside etching technique without compromising the mechanical stability of the chip. The implemented double folded dipole antenna achieves an antenna gain of 6 dBi with a radiation efficiency of 54%. The transceiver is equipped with a 61 GHz VCO that is complemented with a frequency doubler to generate the transmit signal. The receive path includes an LNA, a 90 degree coupler, two passive subharmonic mixers and variable gain amplifiers. Radar measurements with static as well as moving targets were done to show the applicability of the developed system.

  • Q-Band CMOS Transmitter System-on-Chip for Protected Satellite Communication

    This paper reports the first fully integrated millimeter-wave CMOS transmitter system-on-chip (SoC) for protected communication enabling next generation terminals. A 200MHz DDR digital baseband input drives a complex frequency translator with sub-Hz frequency hopping resolution via an on-chip numerically controlled oscillator (NCO). Two 12b RZ DACs and quadrature modulator form a single-side band (SSB) up-converter achieving >30dB spur rejection. An RF up- converter with a X2 multiplier drives a 24dBm Q-band CMOS stacked power amplifier. The SoC was demonstrated in a current AEHF terminal and achieved 5X lower power consumption and size.

  • Simulation-Based Study of the Inserted-Oxide FinFET for Future Low-Power System-on-Chip Applications

    The performance of an evolutionary FinFET design (iFinFET) is compared against that of the bulk FinFET and gate-all-around (GAA) FET via TCAD three- dimensional device simulations. The results show that the iFinFET is a promising candidate for future low-power system-on-chip applications, providing superior electrostatic integrity relative to the FinFET without the additional process complexity and substantial gate capacitance penalty of the GAA FET.

  • Concentrated mesh and fat tree usage efficiency in System-on-Chip based multiprocessor distributed processing architectures

    Distributed Processing Systems (DPS) take sophisticated tasks as input, and process them in a distributed manner using spread resources. In this paper, we evaluate DPS implemented on low-level System-on-Chip (SoC) interconnection architectures: mesh, concentrated mesh and fat tree. We propose autonomous algorithms for nodes and routers and define efficiency metrics that are used later for evaluation. The evaluation is performed by a dedicated experimentation system, in which fully functional DPS is implemented. In this paper, we focus on resource utilization in interconnection networks and also present their energy consumption. Tradeoff between utilization and electrical energy consumption is presented. Research results show that the concentrated mesh is a promising interconnection network suitable to handle the needs of distributed processing systems.

  • Lightweight cryptography on programmable system on chip: Standalone software implementation

    Embedded systems of today are being designed to be highly reliable, to respond to real-time system demands, to have functional flexibility and most importantly to run on low power sources. These ubiquitous systems are nowadays being employed to handle highly sensitive data including global positioning, health, banking and personal data. Based on these trends, the demands on their security mechanism have increased, not only because of newly emerging threats that embedded systems face but also due to the power resource constraints that compels the revisiting of the security approach. Lightweight cryptosystems becomes a feasible option and in this work we implement two lightweight algorithms namely PRESENT and Clefia, together with their counterpart well- known symmetric encryption algorithms AES and 3DES, on a dual core ARM-based system-on-chip (SoC) platform. We observe the dynamics of implementing the algorithms on such a device and study its performance. The implementation was carried out by means of standalone bare metal software implementation that executes directly on the dual core ARM CPU. The result is presented and compared to normal PC-based Linux implementation.

  • System-on-Chip architecture for high-speed data acquisition in visible light communication system

    On this paper, we present results of our research in system-on-chip architecture for digital data acquisition in visible light communication. The objective of this research is to design data acquisition architecture for signal with high speed frequency using system-on-chip based design. The designed system is divided into two subsystems, hardware layer and software layer. All of the hardware resources are implemented on ZYNQ-7000 System-on- Chip, whereas the software is implemented using Xilinx API to establish connection to PC through UDP-based Ethernet connection. The implemented design has been proven to be able to perform high speed data acquisition for certain frequency sampling and able to transmit data to PC for data processing and displaying.



Standards related to System-on-chip

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IEEE Standard Test Interface Language (STIL) for Digital Test Vector Data---Core Test Language (CTL)

Unless the logic inside embedded cores can be merged with the surrounding user-defined logic (UDL), the SoC test requires reuse of test data and test structures specific to individual cores (designs) when integrated into larger systems. This standard defines language constructs sufficient to represent the context of a core and of the integration of that core into a system, to ...


Standard for Extensions to Standard Test Interface Language (STIL) for Semiconductor Design Environments

Structures are defined in STIL to support usage as semiconductor simulation stimulus, including (1) mapping signal names to equivalent design references, (2) interface between scan and built-in self test (BIST) and the logic simulation, (3) data types to represent unresolved states in a pattern, (4) parallel or asynchronous pattern execution on different design blocks, and (5) expression-based conditional execution of ...


Standard for Quality of Electronic and Software Intellectual Property used in System and System on Chip (SoC) Designs

This specification defines a standard XML format for representing electronic IP quality information, based on an information model for electronic IP quality measurement. It includes a schema and the terms that are relevant for measuring electronic IP quality, including software that executes on the system. The schema and information model can be focused to represent particular categories of interest to ...


Standard Testability Method for Embedded Core-based Integrated Circuits

IEEE Std 1500 has developed a standard design-for-testability method for integrated circuits (ICs) containing embedded nonmergeable cores. This method is independent of the underlying functionality of the IC or its individual embedded cores. The method creates the necessary requirements for the test of such ICs, while allowing for ease of interoperability of cores that may have originated from different sources.