Conferences related to Switched-capacitor Circuits; Synthesizers

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2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)

This is a set of five conferences with a focus on wireless components, applications and systems that affect both now and our future lifestyle. The main niche of these conferences is to bring together technologists, circuit designers, system designers and entrepreneurs at a single event. It was and is the place where these worlds meet, where new processes and systems can be benchmarked against the needs of circuit designers at the bleeding edge of RF systems. This is also an area where today's design compromises can trigger tomorrow's advanced technologies, where dreams can become a reality.


2019 IEEE International Conference on Industrial Technology (ICIT)

The scope of the conference will cover, but will not be limited to, the following topics: Robotics; Mechatronics; Industrial Automation; Autonomous Systems; Sensing and artificial perception, Actuators and Micro-nanotechnology; Signal/Image Processing and Computational Intelligence; Control Systems; Electronic System on Chip and Embedded Control; Electric Transportation; Power Electronics; Electric Machines and Drives; Renewable Energy and Smart Grid; Data and Software Engineering, Communication; Networking and Industrial Informatics.


2019 IEEE Radio and Wireless Symposium (RWS)

This is a conference with a focus on wireless components, applications, and systems that impact both our current and future life style. The conference's main niche is to bring together technologists, circuit designers, system designers, and entrepreneurs at a single event. It was and is the place where these worlds meet, where new processes and systems can be benchmarked against the needs of circuit designers at the bleeding edge of RF systems, where today's design compromises can trigger tomorrow's advanced technologies. Where dreams can become a reality. RWS is the cornerstone conference for Radio Wireless Week.


2018 Asia-Pacific Microwave Conference (APMC)

The conference topics include microwave theory and techniques, and their related technologies and applications. They also include active devices and circuits, passive components, wireless systems, EMC and EMI, wireless power transfer and energy harvesting, antennas and propagation, and others.


2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)

Analog Circuits, Digital VLSI Circuits, Neural Networks, Non-Linear System, Computer Aided Design, Communication Systems, Digital Signal Processing, MEMS, Nano-electronics


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Periodicals related to Switched-capacitor Circuits; Synthesizers

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Biomedical Circuits and Systems, IEEE Transactions on

The Transactions on Biomedical Circuits and Systems addresses areas at the crossroads of Circuits and Systems and Life Sciences. The main emphasis is on microelectronic issues in a wide range of applications found in life sciences, physical sciences and engineering. The primary goal of the journal is to bridge the unique scientific and technical activities of the Circuits and Systems ...


Communications Magazine, IEEE

IEEE Communications Magazine was the number three most-cited journal in telecommunications and the number eighteen cited journal in electrical and electronics engineering in 2004, according to the annual Journal Citation Report (2004 edition) published by the Institute for Scientific Information. Read more at http://www.ieee.org/products/citations.html. This magazine covers all areas of communications such as lightwave telecommunications, high-speed data communications, personal communications ...


Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...


Instrumentation and Measurement, IEEE Transactions on

Measurements and instrumentation utilizing electrical and electronic techniques.


Microwave and Wireless Components Letters, IEEE

Published monthly with the purpose of providing fast publication of original and significant contributions relevant to all aspects of microwave/millimeter-wave technology. Emphasis is on devices, components, circuits, guided-wave structures, systems and applications covering the frequency spectrum from microwave and beyond, including submillimeter-waves and infrared.


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Most published Xplore authors for Switched-capacitor Circuits; Synthesizers

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Xplore Articles related to Switched-capacitor Circuits; Synthesizers

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Spur suppression in frequency synthesizer using switched capacitor array

2012 International SoC Design Conference (ISOCC), 2012

In this paper we propose a PLL based frequency synthesizer architecture having low spur. Using an array of switched capacitors and a delay locked loop (DLL), a periodic charge distribution technique to suppress reference spur in the PLL has been adopted. The DLL provides the equispaced M instances at which the capacitor array distributes the charge. For the validation of ...


Design of a 40GHz PLL frequency synthesizer with wide locking range ILFD in 65nm CMOS

2015 International SoC Design Conference (ISOCC), 2015

A 40GHz PLL synthesizer is designed in 65nm CMOS for a 60GHz sliding-IF RF transceiver for IEEE 802.11ad applications. For wide locking range, ILFD employs a 5-bit switched capacitor array and a inductive peaking at the injection FET. The ILFD's locking range is wider than the VCO's tuning range, which ensures the PLL can safely lock across the VCO's full ...


Switched-capacitor interpolator for direct-digital frequency synthesizers

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187), 1998

Direct Digital Frequency Synthesis (DDFS) is an attractive alternative to PLL- based synthesizer architectures, mainly due to a better frequency agility and inferior phase noise. For current technologies such synthesizer architectures typically operate below 100 MHz due to power dissipation constraints and speed limitations. In this paper we propose an alternative architecture that allows a practical speed improvement of DDFS ...


A wide locking range and low phase noise quadrature frequency synthesizer suitable for next generation wireless communication systems

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2016

This paper describes the design of a fully-integrated PLL-based and integer-N quadrature frequency synthesizer (QFS) for Ka, V and E multiband mm-wave applications. A 2-bit switched capacitor array directly controlled by voltage level together with MOS varactor and differential coplanar waveguide (CPW) inductors are used in the quadrature voltage-controlled oscillator (QVCO) to cover the wide frequency tuning range, achieve a ...


Design of wideband LC VCO with small Kvco fluctuation for RFID synthesizer application

2008 11th IEEE International Conference on Communication Technology, 2008

In this paper, a wideband LC VCO with small Kvco fluctuation for RFID synthesizer application is designed using SMIC 0.18 mum standard CMOS process. The switched capacitor array and switched varactor array are used for wideband design. The VCO exhibited Kvco fluctuation of only 29%, which is about one third that of a conventional VCO. The simulation results show that ...


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Educational Resources on Switched-capacitor Circuits; Synthesizers

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IEEE-USA E-Books

  • Spur suppression in frequency synthesizer using switched capacitor array

    In this paper we propose a PLL based frequency synthesizer architecture having low spur. Using an array of switched capacitors and a delay locked loop (DLL), a periodic charge distribution technique to suppress reference spur in the PLL has been adopted. The DLL provides the equispaced M instances at which the capacitor array distributes the charge. For the validation of the concept, an integer-N frequency synthesizer with four times repetition of ripples for 916 MHz output frequency and 2 MHz input reference frequency, has been designed in 180 nm CMOS technology. Cadence Spectre simulation shows output spur improvement, with respect to a conventional architecture, of about 59, 75 and 65 dB respectively at 2, 4, 6 MHz offset frequencies while the spur at 8 MHz offset remains unchanged.

  • Design of a 40GHz PLL frequency synthesizer with wide locking range ILFD in 65nm CMOS

    A 40GHz PLL synthesizer is designed in 65nm CMOS for a 60GHz sliding-IF RF transceiver for IEEE 802.11ad applications. For wide locking range, ILFD employs a 5-bit switched capacitor array and a inductive peaking at the injection FET. The ILFD's locking range is wider than the VCO's tuning range, which ensures the PLL can safely lock across the VCO's full tuning range. Also, a tuned buffer with a boosted Q load is employed to minimize unwanted interaction between the VCO and ILFD's operating frequencies, which also helps widen the PLL's locking range. The PLL synthesizer is designed in 65nm CMOS and its die area is 1.0×1.1mm2.

  • Switched-capacitor interpolator for direct-digital frequency synthesizers

    Direct Digital Frequency Synthesis (DDFS) is an attractive alternative to PLL- based synthesizer architectures, mainly due to a better frequency agility and inferior phase noise. For current technologies such synthesizer architectures typically operate below 100 MHz due to power dissipation constraints and speed limitations. In this paper we propose an alternative architecture that allows a practical speed improvement of DDFS circuits. This consists of using a switched-capacitor (SC) interpolator inserted between the digital-to-analog converter (DAC) and the continuous-time output filter and which allows a relaxation of both the filter selectivity requirements as well as the DAC clock frequency. By choosing an optimum ladder-based architecture for the implementation of such interpolator, the opamps can be designed to settle at the lower input frequency, and thus reducing their own speed and power dissipation requirements, while maintaining low amplitude response variability against component errors.

  • A wide locking range and low phase noise quadrature frequency synthesizer suitable for next generation wireless communication systems

    This paper describes the design of a fully-integrated PLL-based and integer-N quadrature frequency synthesizer (QFS) for Ka, V and E multiband mm-wave applications. A 2-bit switched capacitor array directly controlled by voltage level together with MOS varactor and differential coplanar waveguide (CPW) inductors are used in the quadrature voltage-controlled oscillator (QVCO) to cover the wide frequency tuning range, achieve a good phase noise performance of -105.5dBc/Hz@1MHz offset while realizing a wide tuning range over than 19.26%. Multiband co-tuning (MBCT) technology is proposed to extend the frequency locking range of ILFD. A programmable charge pump is designed to obtain relatively constant bandwidth. The quadrature frequency synthesizer, implemented in IBM 0.13μm CMOS process, can provide over than +0.88dBm output power at 50ohm load from 27.72 to 33.63GHz while drawing 50mA current (not including testing buffers) from 2.5V power supply and 49mA from 1.2V power supply.

  • Design of wideband LC VCO with small Kvco fluctuation for RFID synthesizer application

    In this paper, a wideband LC VCO with small Kvco fluctuation for RFID synthesizer application is designed using SMIC 0.18 mum standard CMOS process. The switched capacitor array and switched varactor array are used for wideband design. The VCO exhibited Kvco fluctuation of only 29%, which is about one third that of a conventional VCO. The simulation results show that the tuning frequency range is 64% from 0.76 GHz to 1.48 GHz, VCO Gain is from 41 MHz to 62 MHz with power consumption of about 9 mW at 1.8 V supply. The measured phase noise is less than -90 dBc/Hz at 100 kHz offset within the entire tuning range.

  • A CMOS fractional-N frequency synthesizer for low-power RF applications

    A divider-free fractional-N CMOS frequency locked loop synthesizer is presented. The frequency divider used in traditional frequency synthesizers is replaced by a switched-capacitor frequency detector (SC-FD). The architecture of the proposed synthesizer has been successfully simulated at behavioral level to verify its expected functionality. Design considerations of various synthesizer building blocks are discussed to highlight their impact on the synthesizer performance.

  • A PLL-based frequency synthesizer for 160-MHz double-sampled SC filters

    This paper describes a clock generator for a double-sampled switched capacitor (SC) filtering system. The circuit is based on a fast charge-pump phase-locked loop (PLL) system that multiplies an external reference clock signal by a factor of eight and also ensures a high precision and stability of two internal nonoverlapped clock phases up to 80 MHz. This allows the driving of double-sampled SC filters up to 160 MHz sampling rate. The PLL is a third- order system with a bandwidth of 100 kHz and a lock-in time of 15 /spl mu/s. The output clock jitter is 170 ps r.m.s. The total power consumption at 160 MHz is 25 mW and the total chip area is about 1 mm/sup 2/.

  • A 1.8 V monolithic CMOS nested-loop frequency synthesizer for GSM receivers at 1.8 GHz

    A low-power, integrated 1.8 GHz nested-loop frequency synthesizer for GSM at 1.8 GHz in a 0.18 /spl mu/m CMOS technology is presented. The synthesizer consists of two voltage-control oscillators (VCOs) and uses band switching MIM capacitors and analog tuning circuits using pMOS capacitors. Both VCOs and loop-filters are integrated on-chip. The IF VCO phase noise is -131 dBc/Hz@600 kHz from a 450 MHz carrier and the RF VCO phase noise is -121 dBc/Hz@600 kHz from a 1.8 GHz carrier. The power consumption of this nested-loop frequency synthesizer is 36 mW@1.8 V and has a die size of 3000 /spl mu/m /spl times/ 2000 /spl mu/m.

  • A low-noise fast-settling PLL frequency synthesizer for CDMA receivers

    A 1.8-2 GHz fully integrated CMOS phase-locked-loop (PLL) frequency synthesizer for CDMA receivers is presented. The design focuses on the voltage controlled oscillator (VCO) and loop bandwidth adaptation technique, which determine the out-of-band phase noise and the speed of the PLL frequency synthesizer, respectively. A low power low phase noise bond wire VCO is proposed. The inductance compensation control circuit combined with the switched-capacitor array is used to automatically compensate the bond wire inductance variation. A novel lock detector that adoptively controls the loop bandwidth is employed. Implemented in a 0.18 /spl mu/m CMOS technology and at a 1.8 V supply voltage, the PLL frequency synthesizer dissipates 24 mW and occupies a chip area of 2.6 mm/spl times/1.6 mm. The simulation results show that phase noise of the synthesizer is -122.6 dBc/Hz at 1 MHz offset frequency and the settling time is 70 /spl mu/s.

  • Switched capacitor PLL frequency synthesizer

    A technique for high resolution frequency synthesizer is introduced and analyzed. This technique is based on a duty cycle controlled oscillator circuit used as a fractional frequency divider placed in the feedback path of a phase locked loop. A design example is given with experimental results.



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