Conferences related to Static Memory

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2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2020 IEEE International Conference on Image Processing (ICIP)

The International Conference on Image Processing (ICIP), sponsored by the IEEE SignalProcessing Society, is the premier forum for the presentation of technological advances andresearch results in the fields of theoretical, experimental, and applied image and videoprocessing. ICIP 2020, the 27th in the series that has been held annually since 1994, bringstogether leading engineers and scientists in image and video processing from around the world.


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.


IECON 2020 - 46th Annual Conference of the IEEE Industrial Electronics Society

IECON is focusing on industrial and manufacturing theory and applications of electronics, controls, communications, instrumentation and computational intelligence.



Periodicals related to Static Memory

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Advanced Packaging, IEEE Transactions on

The IEEE Transactions on Advanced Packaging has its focus on the modeling, design, and analysis of advanced electronic, photonic, sensors, and MEMS packaging.


Aerospace and Electronic Systems Magazine, IEEE

The IEEE Aerospace and Electronic Systems Magazine publishes articles concerned with the various aspects of systems for space, air, ocean, or ground environments.


Automatic Control, IEEE Transactions on

The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...


Circuits and Systems for Video Technology, IEEE Transactions on

Video A/D and D/A, display technology, image analysis and processing, video signal characterization and representation, video compression techniques and signal processing, multidimensional filters and transforms, analog video signal processing, neural networks for video applications, nonlinear video signal processing, video storage and retrieval, computer vision, packet video, high-speed real-time circuits, VLSI architecture and implementation for video technology, multiprocessor systems--hardware and software-- ...


Circuits and Systems I: Regular Papers, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.



Most published Xplore authors for Static Memory

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Xplore Articles related to Static Memory

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A novel SET/MOSFET hybrid static memory cell design

IEEE Transactions on Nanotechnology, 2004

In this paper, a single electron transistor (SET)/metal-oxide-semiconductor field effect transistor (MOSFET)-based static memory cell is proposed. The negative differential conductance (NDC) characteristics of the SET block help us establish the static memory cell circuits more compactly than those in conventional technologies. The proposed memory cell consists of one MOSFET and two back-to-back connected SET blocks exhibiting the NDC. The ...


Negative resistance element for a static memory cell based on enhanced surface generation (MOS devices)

IEEE Electron Device Letters, 1990

A negative resistance (NR) element for a static memory cell using enhanced surface generation of MOS devices is proposed. Such a memory cell will maintain information with extremely small current information and the control circuitry can be the same as in one-transistor dynamic memories. The mechanism of operation is discussed and some experimental data are presented. It is shown that ...


A new design technique of hybrid SET/CMOS static memory cells

2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003., 2003

The single electron transistor(SET)/CMOS-based static memory cell is proposed. The negative differential conductance(NDC) characteristics of SET block help to realize very compact circuits for implementing the static memory cell, compared with the memory cells in conventional technologies. The proposed memory cell consists of one MOSFET and two back-to-back connected SET blocks having the NDC. The peak-to-valley current ratio of the ...


A folded resistor and capacitor (FRC) static memory cell with triple poly-Si structures

1987 Symposium on VLSI Technology, 1987

In order to achieve high packing density Hi-CMOS SRAM's with poly load memory cells, small cell area and low power dissipation are required. When minimising memory cell area, it is important to scale down poly load resistors. Especially for mega bit level SRAM's with battery back up functions, ultra low stand-by power dissipation should be determined by highly resistive poly ...


Optimization of area and power in multi-mode power gating scheme for static memory elements

2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2016

This paper presents an optimization method of area and power for static memory elements by using multi-mode power gating (MMPG) scheme. A 2-transistor MMPG scheme replaces the usual 5-transistor one to effectively reduce on chip area overhead and leakage power, simultaneously combining trimming circuits (TC) to guarantee the safety of data retention. When applying the proposed approach into clean/dirty-cache (CD-cache), ...



Educational Resources on Static Memory

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IEEE.tv Videos

Formula Hybrid
Overcoming the Static Learning Bottleneck - the Need for Adaptive Neural Learning - Craig Vineyard: 2016 International Conference on Rebooting Computing
IMS 2011 Microapps - Memory Effects in RF Circuits: Definition, Manifestations and Fast, Accurate Simulation
From Edge To Core: Memory-Driven Hardware and Software Co-Design - IEEE Rebooting Computing Industry Summit 2017
Fast solution of linear systems with RRAM - Zhong Sun - ICRC San Mateo, 2019
Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
Improved Deep Neural Network Hardware Accelerators Based on Non-Volatile-Memory: the Local Gains Technique: IEEE Rebooting Computing 2017
Array storing and retrieval
Edge Computing and Network Slicing for the Factories of the Future - Future X Network Panel Talk - Andreas Mueller - Brooklyn 5G Summit 2018
Ted Berger: Far Futures Panel - Technologies for Increasing Human Memory - TTM 2018
Non-Volatile Memory Array Based Quantization - Wen Ma - ICRC San Mateo, 2019
Memory Centric Artificial Intelligence - Damien Querlioz at INC 2019
RNSnet: In-Memory Neural Network Acceleration Using Residue Number System - Sahand Salamat - ICRC 2018
Impact of Linearity and Write Noise of Analog Resistive Memory: IEEE Rebooting Computing 2017
High-Bandwidth Memory Interface Design
Future of Computing: Memory/Storage - Steve Pawlowski - ICRC San Mateo, 2019
IRDS: Lithography - Mark Neisser at INC 2019
The Memory of Cars Talk by Tom Coughlin
Erasing Logic-Memory Boundaries in Superconductor Electronics - Vasili Semenov: 2016 International Conference on Rebooting Computing
Rebooting Memory Architecture - Wen-mei Hwu at INC 2019

IEEE-USA E-Books

  • A novel SET/MOSFET hybrid static memory cell design

    In this paper, a single electron transistor (SET)/metal-oxide-semiconductor field effect transistor (MOSFET)-based static memory cell is proposed. The negative differential conductance (NDC) characteristics of the SET block help us establish the static memory cell circuits more compactly than those in conventional technologies. The proposed memory cell consists of one MOSFET and two back-to-back connected SET blocks exhibiting the NDC. The peak-to-valley current ratio of the SET block is above four with C/sub G/=5.4C/sub T/ (C/sub T/=0.1 aF) at T=77K. The read and write operations of the proposed memory cell were validated with SET/MOSFET hybrid simulations at T=77 K. Even though the fabrication process that integrates MOSFET devices and SET blocks with NDC is not yet available, these results suggest that the proposed SET/MOSFET hybrid static memory cell is suitable for a high-density memory system.

  • Negative resistance element for a static memory cell based on enhanced surface generation (MOS devices)

    A negative resistance (NR) element for a static memory cell using enhanced surface generation of MOS devices is proposed. Such a memory cell will maintain information with extremely small current information and the control circuitry can be the same as in one-transistor dynamic memories. The mechanism of operation is discussed and some experimental data are presented. It is shown that in order to maintain information in a single static memory cell, the required current can be as low as a few picoamperes. Operating currents are large enough to compensate for leakage currents of storage capacitors in dynamic RAM (DRAM) memories. By adding the proposed circuit in parallel with those capacitors, the dynamic memory can be converted into a static memory requiring no refresh circuit or restoring circuit. In the proposed memory structure, the storage capacitor can be reduced significantly or perhaps even eliminated. This will result in much faster operation in comparison to DRAM memories.<<ETX>>

  • A new design technique of hybrid SET/CMOS static memory cells

    The single electron transistor(SET)/CMOS-based static memory cell is proposed. The negative differential conductance(NDC) characteristics of SET block help to realize very compact circuits for implementing the static memory cell, compared with the memory cells in conventional technologies. The proposed memory cell consists of one MOSFET and two back-to-back connected SET blocks having the NDC. The peak-to-valley current ratio of the SET block is above 5 with C/sub G/=5.4C/sub T/(C/sub T/=0.1aF) at T=77K. A read and write operation of the proposed memory cell was validated with SET/CMOS hybrid simulation at T=77K. Even though the fabrication process which integrate MOSFET devices and SET block with NDC is not available, these results suggest that the proposed SET/CMOS static memory cell is suitable for a high density memory system with the low power consumption.

  • A folded resistor and capacitor (FRC) static memory cell with triple poly-Si structures

    In order to achieve high packing density Hi-CMOS SRAM's with poly load memory cells, small cell area and low power dissipation are required. When minimising memory cell area, it is important to scale down poly load resistors. Especially for mega bit level SRAM's with battery back up functions, ultra low stand-by power dissipation should be determined by highly resistive poly loads in memory cells. Moreover, alpha particle induced soft errors are also one of major problems for developing high density SRAM's. To solve these problems, a newly developed folded resistor and capacitor (FRC) memory cell has been proposed. The features of the newly proposed memory cells are (1) highly resistive poly loads with folded poly structures to achieve ultra low stand-by power and (2) stacked capacitors added to the storage nodes to suppress soft errors. This paper describes the FRC memory cell structures, characteristics of folded poly loads and stacked capacitors fabricated by submicron CMOS process.

  • Optimization of area and power in multi-mode power gating scheme for static memory elements

    This paper presents an optimization method of area and power for static memory elements by using multi-mode power gating (MMPG) scheme. A 2-transistor MMPG scheme replaces the usual 5-transistor one to effectively reduce on chip area overhead and leakage power, simultaneously combining trimming circuits (TC) to guarantee the safety of data retention. When applying the proposed approach into clean/dirty-cache (CD-cache), we can reduce area overhead and leakage power consumption. The simulation results show that the area overhead of SRAM with the proposed approach is reduced from 33.4% to 21.8% compared to that of SRAM with usual MMPG. On the other hand, leakage power is reduced by 12.35% compared to SRAM with usual MMPG and by 86.77% compared to SRAM without power gating scheme. Moreover, the ability of noise immunity of SRAM with proposed approach can also be improved.

  • Dynamic wordline voltage swing for low leakage and stable static memory banks

    A new SRAM circuit technique based on dynamically adjusting the wordline voltage swing is proposed in this paper for reducing the leakage power consumption and enhancing the data stability in static memory banks. With the proposed technique, the wordline voltage swing is reduced in order to suppress the voltage disturbance at the data storage nodes during a read operation. The stability of a minimum sized standard six transistors (6T) SRAM cell is thereby significantly enhanced. Alternatively, during a write operation the wordline signal has a full voltage swing in order to achieve write-ability with a high write margin. With the proposed circuit technique, the static noise margin is enhanced by up to 122% as compared to the conventional full- voltage-swing 6T SRAM circuits with minimum sized transistors. Furthermore, the leakage power consumption with the proposed technique is reduced by 51% as compared to the conventional full-voltage-swing circuits sized for data stability in a 65nm CMOS technology.

  • Spike based learning with weak multi-level static memory

    In this paper we present a VLSI implementation of learning synapse that that uses a spike based learning rule to adjust its weight. The weight is stored on a recently presented weak multi-level static memory cell (MLSM) by Hafliger and Riis (see ibid., May 2003). This memory cell stores a voltage on a capacitance and that voltage is weakly driven to the closest of several stable levels. We verified the suitability of this memory for this task in a VLSI chip implementation. An array of integrate and fire neurons with four of these learning synapse each was implemented on a 0.6 /spl mu/m AMS CMOS chip. The learning capability of these neurons was tested in simple spike and rate based pattern recognition tasks in a two neuron network. Cross-inhibition between them lead to improved decorrelation of the output spikes, inducing a tendency in the neurons to specialize on different patterns.

  • A static memory cell based on the negative resistance of the gate terminal of p-n-p-n devices

    We propose a new static memory cell that is based on bistable operation of a three-terminal p-n-p-n device working in the blocking state. The bistable operation is verified by the measurements of Si/amorphous Si prototypes. The experimental prototypes achieve delay times in the nanosecond range when operating with external gate and anode resistors. In order to decrease the power consumption of the memory cell, we propose to operate it with MOS transistor switches instead of the gate resistors. The memory cell can be integrated into VLSI processes, and is of a size suitable for VLSI applications.<<ETX>>

  • Static memory element based on electron Y-branch switch

    A compact memory element, based on an electron Y-branch switch, has been realised. Memory operation is a result of bilateral feedback coupling of each of the branches to the opposing side-gate. D-flip-flop in addition to RS-flip- flop operation is demonstrated.

  • Selection of operation mode on SOI/MOSFETs for high-resistivity load static memory cell

    SOI/MOSFETs are widely known to have some advantages such as reduction of parasitic capacitance, improvement of subthreshold characteristics and increased drive current, compared with bulk-Si/MOSFETs. Moreover, this structure provides the reduction in the substrate-bias effect because the back-gate bias (Si substrate) is applied to the channel region through thick buried oxide. In the present paper, we propose the best choice of operation mode of SOI/MOSFETs in a high-resistivity load SRAM cell to improve the stability in the memory cell and to obtain sufficient static noise margin providing non-destructive reading of cell data at low supply voltage.<<ETX>>



Standards related to Static Memory

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No standards are currently tagged "Static Memory"