Conferences related to Shapes Checking

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2021 IEEE International Conference on Fuzzy Systems (FUZZ-IEEE)

FUZZ-IEEE 2021 will represent a unique meeting point for scientists and engineers, both from academia and industry, to interact and discuss the latest enhancements and innovations in the field. The topics of the conference will cover all the aspects of theory and applications of fuzzy sets, fuzzy logic and associated approaches (e.g. aggregation operators such as the Fuzzy Integral), as well as their hybridizations with other artificial and computational intelligence techniques.


2020 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC)

The conference program will consist of plenary lectures, symposia, workshops and invitedsessions of the latest significant findings and developments in all the major fields of biomedical engineering.Submitted papers will be peer reviewed. Accepted high quality papers will be presented in oral and postersessions, will appear in the Conference Proceedings and will be indexed in PubMed/MEDLINE


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)


2020 IEEE International Conference on Consumer Electronics (ICCE)

The International Conference on Consumer Electronics (ICCE) is soliciting technical papersfor oral and poster presentation at ICCE 2018. ICCE has a strong conference history coupledwith a tradition of attracting leading authors and delegates from around the world.Papers reporting new developments in all areas of consumer electronics are invited. Topics around the major theme will be the content ofspecial sessions and tutorials.


2020 IEEE International Conference on Image Processing (ICIP)

The International Conference on Image Processing (ICIP), sponsored by the IEEE SignalProcessing Society, is the premier forum for the presentation of technological advances andresearch results in the fields of theoretical, experimental, and applied image and videoprocessing. ICIP 2020, the 27th in the series that has been held annually since 1994, bringstogether leading engineers and scientists in image and video processing from around the world.


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Periodicals related to Shapes Checking

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Antennas and Propagation, IEEE Transactions on

Experimental and theoretical advances in antennas including design and development, and in the propagation of electromagnetic waves including scattering, diffraction and interaction with continuous media; and applications pertinent to antennas and propagation, such as remote sensing, applied optics, and millimeter and submillimeter wave techniques.


Applied Superconductivity, IEEE Transactions on

Contains articles on the applications and other relevant technology. Electronic applications include analog and digital circuits employing thin films and active devices such as Josephson junctions. Power applications include magnet design as well asmotors, generators, and power transmission


Automatic Control, IEEE Transactions on

The theory, design and application of Control Systems. It shall encompass components, and the integration of these components, as are necessary for the construction of such systems. The word `systems' as used herein shall be interpreted to include physical, biological, organizational and other entities and combinations thereof, which can be represented through a mathematical symbolism. The Field of Interest: shall ...


Biomedical Engineering, IEEE Transactions on

Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.


Broadcasting, IEEE Transactions on

Broadcast technology, including devices, equipment, techniques, and systems related to broadcast technology, including the production, distribution, transmission, and propagation aspects.


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Most published Xplore authors for Shapes Checking

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Xplore Articles related to Shapes Checking

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Constellation Shaping for Bit-Interleaved LDPC Coded APSK

IEEE Transactions on Communications, 2012

An energy-efficient approach is presented for shaping a bit-interleaved low- density parity-check (LDPC) coded amplitude phase-shift keying (APSK) system. A subset of the interleaved bits output by a binary LDPC encoder are passed through a nonlinear shaping encoder whose output is more likely to be a zero than a one. The "shaping" bits are used to select from among a ...


Spectral Shape of Check-Hybrid GLDPC Codes

2010 IEEE International Conference on Communications, 2010

This paper analyzes the asymptotic exponent of both the weight spectrum and the stopping set size spectrum for a class of generalized low-density parity- check (GLDPC) codes. Specifically, all variable nodes (VNs) are assumed to have the same degree (regular VN set), while the check node (CN) set is assumed to be composed of a mixture of different linear block ...


Development of Cu-Zn-Al based shape memory alloy

2017 Fifth International Conference on Aerospace Science & Engineering (ICASE), 2017

Shape Memory Alloys (SMA) has intriguing attributes of recovering apparent permanent deformations to about 10% and above. In addition, these are metal alloys and display typical features of metals like resistance, stiffness, and workability etc. The blend of all these properties makes it easy to know why these materials are smart in the grounds of engineering and ascend to a ...


Three and four-dimensional parity-check codes for correction and detection of multiple errors

International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004., 2004

We examine two different schemes of three dimensional parity checking codes that can be obtained by arranging the information and parity bits as a combination of rows and columns or by arranging them as two dimensional planes to obtain a three dimensional cube. Finding the number of errors detected and the numbers of errors corrected has been the main aim ...


Hybrid Probabilistic-Geometric-Shaped 8-PAM Suitable for Data Centers’ Communication

2018 Asia Communications and Photonics Conference (ACP), 2018

We propose a hybrid probabilistic-geometric-shaped (HPGS) 8-PAM signaling scheme, as a candidate suitable for data centers' communications. The properly chosen HPGS 8-PAM parameters for different SNR-regions allows us to closely approach the Shannon limit. We demonstrate that LPDC-coded HPGS 8-PAM outperforms both probabilistic-shaped and uniform LDPC-coded 8-PAM schemes.


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Educational Resources on Shapes Checking

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IEEE-USA E-Books

  • Constellation Shaping for Bit-Interleaved LDPC Coded APSK

    An energy-efficient approach is presented for shaping a bit-interleaved low- density parity-check (LDPC) coded amplitude phase-shift keying (APSK) system. A subset of the interleaved bits output by a binary LDPC encoder are passed through a nonlinear shaping encoder whose output is more likely to be a zero than a one. The "shaping" bits are used to select from among a plurality of subconstellations, while the unshaped bits are used to select the symbol within the subconstellation. Because the shaping bits are biased, symbols from lower-energy subconstellations are selected more frequently than those from higher-energy subconstellations. An iterative decoder shares information among the LDPC decoder, APSK demapper, and shaping decoder. Information rates are computed for a discrete set of APSK ring radii and shaping bit probabilities, and the optimal combination of these parameters is identified for the additive white Gaussian noise (AWGN) channel. With the assistance of extrinsic- information transfer (EXIT) charts, the degree distributions of the LDPC code are optimized for use with the shaped APSK constellation. Simulation results show that the combination of shaping, degree-distribution optimization, and iterative decoding can achieve a gain in excess of 1 dB in AWGN at a rate of 3 bits/symbol compared with a system that does not use shaping, uses an unoptimized code from the DVB-S2 standard, and does not iterate between decoder and demodulator.

  • Spectral Shape of Check-Hybrid GLDPC Codes

    This paper analyzes the asymptotic exponent of both the weight spectrum and the stopping set size spectrum for a class of generalized low-density parity- check (GLDPC) codes. Specifically, all variable nodes (VNs) are assumed to have the same degree (regular VN set), while the check node (CN) set is assumed to be composed of a mixture of different linear block codes (hybrid CN set). A simple expression for the exponent (which is also referred to as the growth rate or the spectral shape) is developed. This expression is consistent with previous results, including the case where the normalized weight or stopping set size tends to zero. Furthermore, it is shown how certain symmetry properties of the local weight distribution at the CNs induce a symmetry in the overall weight spectral shape function.

  • Development of Cu-Zn-Al based shape memory alloy

    Shape Memory Alloys (SMA) has intriguing attributes of recovering apparent permanent deformations to about 10% and above. In addition, these are metal alloys and display typical features of metals like resistance, stiffness, and workability etc. The blend of all these properties makes it easy to know why these materials are smart in the grounds of engineering and ascend to a new way of thoughts about the design of mechanical systems. The present study aims to develop Cu-Zn-Al based shape memory alloy by melting route, finding out the transformation temperatures and the development of shape memory effect. The design and methodology approach includes the mixture of test material which is chips of pure Copper (99.9%), Zinc (99%) and Aluminum (85%). All these chips are mixed and melted. Furthermore, the melt was die casted in open air in a capsule shape. X-ray fluorescence (XRF) was carried out to check the estimated composition and afterwards spectroscopy was done to check the actual composition of the alloy. In addition, the alloy, in a capsule form, was cold rolled up to 1 mm thickness with inter pass annealing at 350°C to form a wire. After that the thermal properties of the wire were examined by a custom made experiment following the principles of Differential Scanning Calorimeter (DSC). The final wire was then heat treated 830°C for 18 minutes followed by step quenching and then aging at 150°C for 90 minutes followed by quenching to induce the shape memory effect (SME) in the alloy.

  • Three and four-dimensional parity-check codes for correction and detection of multiple errors

    We examine two different schemes of three dimensional parity checking codes that can be obtained by arranging the information and parity bits as a combination of rows and columns or by arranging them as two dimensional planes to obtain a three dimensional cube. Finding the number of errors detected and the numbers of errors corrected has been the main aim of this work. The code rate and the overhead of each scheme has been calculated and compared with that of the standard parity schemes available. Some general equations have been derived to represent these families of codes. A four dimensional scheme that can detect and correct more multiple errors has also been discussed.

  • Hybrid Probabilistic-Geometric-Shaped 8-PAM Suitable for Data Centers’ Communication

    We propose a hybrid probabilistic-geometric-shaped (HPGS) 8-PAM signaling scheme, as a candidate suitable for data centers' communications. The properly chosen HPGS 8-PAM parameters for different SNR-regions allows us to closely approach the Shannon limit. We demonstrate that LPDC-coded HPGS 8-PAM outperforms both probabilistic-shaped and uniform LDPC-coded 8-PAM schemes.

  • A Hybrid Admissible Distortion Checking Algorithm for the B-Spline-Based Operational Rate-Distortion Optimal Shape Coding

    Admissible distortion checking algorithm plays a very important role in both rate distortion performance and computational efficiency of B-spline-based operational rate-distortion optimal shape coding framework under the minimum- maximum criterion. Existing distortion measurement using chord-length parameterization (DMCLP) is fast but results in extra bit-rate problem. In contrast, the up to date accurate distortion measurement using analytical model (ADMAM) can achieve the smallest bit-rate but is very time consuming. It motivates us to develop a hybrid admissible checking algorithm that can take full use of each advantage. Recalling the definitions of both DMCLP and ADMAM for each associated contour point, the authors show that DMCLP is the distance from the parameterized B-spline point while ADMAM is the shortest distance from the approximating B-splines.

  • Shape-based recognition and classification for common objects - an application in video scene analysis

    In this paper, a new system that can recognize and classify the common objects found in a video scene into four object classes, which are four legs animal, vehicle, human, and others object classes, is presented. To classify the objects, the shape features of the objects are extracted from the input images of objects in binary silhouette form. Then, the features are applied to the classification algorithm, which consists of two descriptive ratio tests and one shape test to classify the objects into different categories. Firstly, Width to Height Ratio test (WTHR) is used to differentiate between two groups of objects, four legs animal and vehicle in one group, human and others objects in another group. Subsequently, Base to Abdomen Ratio test (BTAR) is used to differentiate between animal and vehicle objects while Shape Boundary Test (SBT) is used to differentiate the human object from others objects. The proposed system is tested with different dataset containing the common objects listed in above with different pose and position, to check for the system performance and system accuracy. 73.33% accuracy is achieved for Animal object class, 86.67% accuracy for Vehicle object class, 93.33% accuracy for Human object class, and 86.67% accuracy for others object class. An overall recognition rate of approximately 86.67% is achieved.

  • A new algorithm of counting the number of small stopping sets and girth in QC-LDPC Codes

    It is well known that the performance of low-density parity check (LDPC) codes under iterative decoding is determined by certain combinatorial structures (such as stopping sets and girth) in the Tanner graph. The difficulty in enumerating all possible combinations of the columns may prevent an efficient search of good LDPC codes with small stopping sets and girth. To solve the problem, this paper presents a new algorithm of counting the number of small stopping sets and girth by analyzing the shapes of the cycles of Tanner graph in parity check matrix for designing good LDPC codes which is less complex than the existing algorithms. This method can be used effectively to evaluate the performance of LDPC codes according to their small stopping sets and girth distributions.

  • Technology of dispensing check based-on tablet features

    This paper designs and realizes a bagged tablets checking system. First, according to tablet characteristics, color feature library and shape feature library are created. Second, the tablet image is clustered by K-means algorithm. And threshold segmentation for the tablet image use Ostu method. Finally, the recognition result of sorts of tablets in bag will compare with prescription in database written by doctor in order to check the dispensing correctness. The experiments' results show that the dispensing check is effective.

  • Protograph-Based LDPC Code Design for Shaped Bit-Metric Decoding

    A protograph-based low-density parity-check (LDPC) code design technique for bandwidth-efficient coded modulation with probabilistic shaping is presented. The approach jointly optimizes the LDPC code node degrees and the mapping of the coded bits to the bit-interleaved coded modulation (BICM) bit-channels. For BICM with uniform inputs and for BICM with probabilistic shaping, binary- input symmetric-output surrogate channels for the code design are used. The constructed codes for uniform inputs perform as good as the multi-edge type codes of Zhang and Kschischang (2013). For 8-ASK and 64-ASK with probabilistic shaping, codes of rates 2/3 and 5/6 with blocklength 64800 are designed, which operate within 0.63 and 0.69 dB of 1/2 log2(1 + SNR) for a target frame error rate of 10-3at spectral 1 efficiencies of 1.38 and 4.25 bits/channel use, respectively.



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