Conferences related to Phase change Memory

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2020 IEEE International Solid- State Circuits Conference - (ISSCC)

ISSCC is the foremost global forum for solid-state circuits and systems-on-a-chip. The Conference offers 5 days of technical papers and educational events related to integrated circuits, including analog, digital, data converters, memory, RF, communications, imagers, medical and MEMS ICs.


2020 IEEE International Symposium on Circuits and Systems (ISCAS)

The International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premier networking and exchange forum for researchers in the highly active fields of theory, design and implementation of circuits and systems. ISCAS2020 focuses on the deployment of CASS knowledge towards Society Grand Challenges and highlights the strong foundation in methodology and the integration of multidisciplinary approaches which are the distinctive features of CAS contributions. The worldwide CAS community is exploiting such CASS knowledge to change the way in which devices and circuits are understood, optimized, and leveraged in a variety of systems and applications.


2020 Joint Conference of the IEEE International Frequency Control Symposium and International Symposium on Applications of Ferroelectrics (IFCS-ISAF)

Ferroelectric materials and applications


2020 57th ACM/ESDA/IEEE Design Automation Conference (DAC)

The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 1996 33rd ACM/IEEE Design Automation Conference (DAC)

  • 1997 34th ACM/IEEE Design Automation Conference (DAC)

  • 1998 35th ACM/IEEE Design Automation Conference (DAC)

  • 1999 36th ACM/IEEE Design Automation Conference (DAC)

  • 2000 37th ACM/IEEE Design Automation Conference (DAC)

  • 2001 38th ACM/IEEE Design Automation Conference (DAC)

  • 2002 39th ACM/IEEE Design Automation Conference (DAC)

  • 2003 40th ACM/IEEE Design Automation Conference (DAC)

  • 2004 41st ACM/IEEE Design Automation Conference (DAC)

  • 2005 42nd ACM/IEEE Design Automation Conference (DAC)

  • 2006 43rd ACM/IEEE Design Automation Conference (DAC)

  • 2007 44th ACM/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier Electronic Design Automation (EDA) and silicon solution event. DAC features over 50 technical sessions covering the latest in design methodologies and EDA tool developments and an Exhibition and Demo Suite area with over 250 of the leading EDA, silicon and IP Providers.

  • 2008 45th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 250 of the leading electronics design suppliers.

  • 2009 46th ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC is the premier event for the electronic design community. DAC offers the industry s most prestigious technical conference in combination with the biggest exhibition, bringing together design, design automation and manufacturing market influencers.

  • 2010 47th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers.

  • 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference is the world s leading technical conference and tradeshow on electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business.

  • 2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. DAC features a wide array of technical presentations plus over 200 of the leading electronics design suppliers

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 session on design methodologies and EDA tool developments, keynotes, panels, plus User Track presentations. A diverse worldwide community representing more than 1,000 organization attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

    DAC Description for TMRF The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading

  • 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2019 56th ACM/ESDA/IEEE Design Automation Conference (DAC)

    EDA (Electronics Design Automation) is becoming ever more important with the continuous scaling of semiconductor devices and the growing complexities of their use in circuits and systems. Demands for lower-power, higher-reliability and more agile electronic systems raise new challenges to both design and design automation of such systems. For the past five decades, the primary focus of research track at DAC has been to showcase leading-edge research and practice in tools and methodologies for the design of circuits and systems.

  • 2021 58th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.

  • 2022 59th ACM/ESDA/IEEE Design Automation Conference (DAC)

    The world's premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, keynotes, panels, plus the NEW User Track presentations. A diverse worldwide community representing more than 1,000 organizations attends each year, from system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities.


2020 IEEE International Electron Devices Meeting (IEDM)

the IEEE/IEDM has been the world's main forum for reporting breakthroughs in technology, design, manufacturing, physics and the modeling of semiconductors and other electronic devices. Topics range from deep submicron CMOS transistors and memories to novel displays and imagers, from compound semiconductor materials to nanotechnology devices and architectures, from micromachined devices to smart -power technologies, etc.



Periodicals related to Phase change Memory

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Biomedical Engineering, IEEE Transactions on

Broad coverage of concepts and methods of the physical and engineering sciences applied in biology and medicine, ranging from formalized mathematical theory through experimental science and technological development to practical clinical applications.


Circuits and Systems II: Express Briefs, IEEE Transactions on

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.


Communications, IEEE Transactions on

Telephone, telegraphy, facsimile, and point-to-point television, by electromagnetic propagation, including radio; wire; aerial, underground, coaxial, and submarine cables; waveguides, communication satellites, and lasers; in marine, aeronautical, space and fixed station services; repeaters, radio relaying, signal storage, and regeneration; telecommunication error detection and correction; multiplexing and carrier techniques; communication switching systems; data communications; and communication theory. In addition to the above, ...


Computer

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed technical content that covers all aspects of computer science, computer engineering, technology, and applications. Computer is a resource that practitioners, researchers, and managers can rely on to provide timely information about current research developments, trends, best practices, and changes in the profession.


Computer Architecture Letters

Rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessors computer systems, computer architecture workload characterization, performance evaluation and simulation techniques, and power-aware computing



Most published Xplore authors for Phase change Memory

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Xplore Articles related to Phase change Memory

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Characteristics of a highly scalable bridge phase change memory

2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008

Recent advances of a highly scalable bridge phase change memory cell are presented. To fabricate and characterize highly scaled devices, designs in both the process procedure and the testing algorism are considered extensively. We also compare the characteristics of the devices made from different types of materials. The experimental data reveal the superior scaling properties of the bridge phase change ...


A simple new write scheme for low latency operation of phase change memory

2012 Symposium on VLSI Technology (VLSIT), 2012

The behavior of resistance drift after RESET operation for phase change memory (PCRAM) is investigated. We propose, for the first time, an effective way to accelerate the drift so that the program/read latency may better match that for DRAM for SCM (storage class memory) application. By simply applying an extra annealing pulse after RESET we can quickly anneal out many ...


Voltage-Controlled Relaxation Oscillations in Phase-Change Memory Devices

IEEE Electron Device Letters, 2008

A new oscillation behavior in a phase-change memory device is presented and analyzed. The device consists in a chalcogenide resistor with a parallel capacitance and no inductance. Biasing the device immediately after a proper trigger pulse leads to damped relaxation oscillations, which can be controlled in frequency by the bias voltage. The oscillation mechanism is explained by repetitive cycles of ...


Internal Temperature Extraction in Phase-Change Memory Cells During the Reset Operation

IEEE Electron Device Letters, 2012

The phase-change memory technology is based on a chalcogenide compound able to reversibly switch between two stable states, namely, an amorphous high- resistive state and a crystalline low-resistive one, enabling the storage of the logical bit. Such phase transition is made by electrical pulses delivered to the memory cell, able to force a temperature raise within the material and to ...


The Impact of Thermal Boundary Resistance in Phase-Change Memory Devices

IEEE Electron Device Letters, 2008

Thermal conduction governs the writing time and energy of phase-change memory (PCM) devices. Recent measurements demonstrated large thermal resistances at the interfaces of phase-change materials with neighboring electrode and passivation materials. In this letter, electrothermal simulations quantify the impact of these resistances on the set to reset transition. The programming current decreases strongly with increasing boundary resistance due to increased ...



Educational Resources on Phase change Memory

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IEEE.tv Videos

Accelerating Machine Learning with Non-Volatile Memory: Exploring device and circuit tradeoffs - Pritish Narayanan: 2016 International Conference on Rebooting Computing
IMS 2014: Out-of-Plane and Inline RF Switches based on Ge2Sb2Te5 Phase-Change Material
A 28GHz SiGe BiCMOS Phase Invariant VGA: RFIC Industry Showcase
IMS 2011 Microapps - Ultra Low Phase Noise Measurement Technique Using Innovative Optical Delay Lines
Q&A: Far Futures Panel - TTM 2018
IMS 2012 Microapps - Phase Noise Choices in Signal Generation: Understanding Needs and Tradeoffs Riadh Said, Agilent
Superconductive Energy-Efficient Computing - ASC-2014 Plenary-series - 6 of 13 - Wednesday 2014/8/13
Micro-Apps 2013: Determining Circuit Material Dielectric Constant from Phase Measurements
From Edge To Core: Memory-Driven Hardware and Software Co-Design - IEEE Rebooting Computing Industry Summit 2017
Winds of Change: Part 1 - The Technology
Phase Retrieval with Application to Optical Imaging
Winds of Change: Part 6 - Looking Ahead
A 40GHz PLL with -92.5dBc/Hz In-Band Phase Noise and 104fs-RMS-Jitter: RFIC Interactive Forum 2017
Improved Deep Neural Network Hardware Accelerators Based on Non-Volatile-Memory: the Local Gains Technique: IEEE Rebooting Computing 2017
Towards Logic-in-Memory circuits using 3D-integrated Nanomagnetic Logic - Fabrizio Riente: 2016 International Conference on Rebooting Computing
IMS 2011 Microapps - Memory Effects in RF Circuits: Definition, Manifestations and Fast, Accurate Simulation
An Analysis of Phase Noise Requirements for Ultra-Low-Power FSK Radios: RFIC Interactive Forum 2017
Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic: IEEE Rebooting Computing 2017
The Art of Parameter Tuning and How it Can Change EC Practice 1
2013 IEEE Presidents' Change The World Competition Winners

IEEE-USA E-Books

  • Characteristics of a highly scalable bridge phase change memory

    Recent advances of a highly scalable bridge phase change memory cell are presented. To fabricate and characterize highly scaled devices, designs in both the process procedure and the testing algorism are considered extensively. We also compare the characteristics of the devices made from different types of materials. The experimental data reveal the superior scaling properties of the bridge phase change memory in different materials.

  • A simple new write scheme for low latency operation of phase change memory

    The behavior of resistance drift after RESET operation for phase change memory (PCRAM) is investigated. We propose, for the first time, an effective way to accelerate the drift so that the program/read latency may better match that for DRAM for SCM (storage class memory) application. By simply applying an extra annealing pulse after RESET we can quickly anneal out many defects (that are responsible for the drift) and provide a drift-free period that enlarges the read window. A physical model is proposed to understand the defect annealing phenomenon, which predicts the resistance drift behavior well.

  • Voltage-Controlled Relaxation Oscillations in Phase-Change Memory Devices

    A new oscillation behavior in a phase-change memory device is presented and analyzed. The device consists in a chalcogenide resistor with a parallel capacitance and no inductance. Biasing the device immediately after a proper trigger pulse leads to damped relaxation oscillations, which can be controlled in frequency by the bias voltage. The oscillation mechanism is explained by repetitive cycles of threshold switching and recovery of the high-resistance (off) state of the amorphous chalcogenide region in the device. Damping is explained by oscillation-induced phase change in the chalcogenide layer.

  • Internal Temperature Extraction in Phase-Change Memory Cells During the Reset Operation

    The phase-change memory technology is based on a chalcogenide compound able to reversibly switch between two stable states, namely, an amorphous high- resistive state and a crystalline low-resistive one, enabling the storage of the logical bit. Such phase transition is made by electrical pulses delivered to the memory cell, able to force a temperature raise within the material and to allow the temperature conditions required for the phase change. The cell internal temperature needs accurate control, and the evaluation of the thermal resistance of the memory cell represents a milestone to develop thermally efficient cell architectures and to gain insights into the thermal properties of the phase-change material. An experimental method for cell internal temperature evaluation has been developed and then supported by the electrothermal simulation of the cell behavior during the program operation, allowing for scaling predictions.

  • The Impact of Thermal Boundary Resistance in Phase-Change Memory Devices

    Thermal conduction governs the writing time and energy of phase-change memory (PCM) devices. Recent measurements demonstrated large thermal resistances at the interfaces of phase-change materials with neighboring electrode and passivation materials. In this letter, electrothermal simulations quantify the impact of these resistances on the set to reset transition. The programming current decreases strongly with increasing boundary resistance due to increased lateral temperature uniformity, which cannot be captured using a reduced effective conductivity in the phase-change material. Reductions in programming current from 20% to 30% occur for an interface resistance of 50 m<sup>2</sup>middotK/GW. The precise spatial distribution of thermal properties is critical for the simulation of PCM devices.

  • Characteristics of TeGa<formula formulatype="inline"><tex Notation="TeX">$_{2}$</tex></formula>Sb<formula formulatype="inline"><tex Notation="TeX">$_{14}$</tex></formula>Thin Films for Phase-Change Memory

    Thin films based on ternary Te-Ga-Sb alloys show much improvement over conventional Ge2Sb2TeB for phase-change memory ap plications in our earlier researches. Disclosed in this paper are phase-change characteristics of a Sb- enriched composition TeGa2Sb14. The crystallization temperature (Tc) determined from electrical resistivity versus temperature curve is 232°C. The activation energy of crystallization (Ec) evaluated by isothermal method is 3.66 eV. Data-retention is 143°C for 10 years attained from the extrapolation of the isothermal Arrhenius plot. The structure of the TeGa2Sb14films analyzed using grazing-incident-angle X-ray diffraction shows amorphous at as-deposited state and one crystalline phase well fitted by R3m Sb-structure after crystallization. Phase-change memory bridge-cells based on TeGa2Sb14film and TiN electrodes fabricated using focus-ion-beam method reveal typical characteristics of memory-switching behaviors suitable for phase-change memory.

  • Wet-etching characteristics of Ge/sub 2/Sb/sub 2/Te/sub 5/ thin films for phase-change memory

    Etching of phase-change memory thin films is essential in the processing for the manufacture of devices. The Ge/sub 2/Sb/sub 2/Te/sub 5/ thin film as a typical material for such purposes can be control-etched by an aqueous solution of 20% nitric acids (HNO/sub 3/). It was found that the Ge/sub 2/Sb/sub 2/Te/sub 5/ films in amorphous state could be etched more uniformly than that in crystalline state. The etch rate can be well controlled to be 4.6 nm/s using such a solution, resulting in macroscopic and microscopic uniformity on amorphous films. It is therefore suggested that the crystallization annealing of Ge/sub 2/Sb/sub 2/Te/sub 5/ thin films should be done after a wet etching process in the manufacture of phase-change random access memories.

  • RESET Distribution Improvement of Phase Change Memory: The Impact of Pre-Programming

    Some nonvolatile phase change memory (PCM) cells with 80-nm heating electrodes are found very difficult to RESET at 3 mA, which directly affects the RESET distribution of the PCM. The large crystal grains with hexagonal structure in the active phase change area, discovered by transmission electron microscope, are the major reason. One preprogramming testing method is introduced, and the resistance distributions of the PCM cells before and after preprogramming are presented. Results show that the large hexagonal crystal grains have been eliminated, thus the resistance distributions have been greatly improved after preprogramming.

  • Analysis of Temperature in Phase Change Memory Scaling

    We analyze constant-voltage isotropic and non-isotropic scaling issues for phase change memory (PCM) based on electrothermal physics. Various analytical and simulation models of general and typical PCM cells that support the analysis is also provided. The analysis shows that the maximum temperature in the PCM cell, which is a key parameter for PCM operation, is independent of geometrical sizes and depends only on the voltage and material properties. This leads to the minimum programming voltage concept, which is determined by material properties of the phase change material. Constant-voltage scaling, electrothermal modeling, ovonic unified memory (OUM), phase change memory (PCM, phase change random access memory, PRAM), proximity disturbance, thermal disturbance.

  • Cross-point phase change memory with 4F<sup>2</sup> cell size driven by low-contact-resistivity poly-Si diode

    We have fabricated the cross-point phase change memory with a selection diode made of poly-Si. The selection diode was fabricated using a low-thermal-budget process that achieved low contact resistivity, high on-current density of 8 MA/cm2 and low off-current density of 100 A/cm2. The improvement in the properties of poly-Si diode makes the set/reset operation of the cross-point 4F2 cell possible, leading to the size reduction of phase change memory chip.



Standards related to Phase change Memory

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No standards are currently tagged "Phase change Memory"